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asahi kasei [ak4632] ms0396-e-00 2005/06 - 1 - general description the ak4632 is a 16-bit mono codec with microphone-amplifier, speaker-amplifier and video- amplifier. input circuits include a microphone-amplifier and an alc (automatic level control) circuit. output circuits include a speaker-amplifier and mono line output. video circuits include a lpf and video-amplifier. the ak4632 suits a moving picture of digital still camera and etc. this speaker-amplifier supports a piezo speaker. the ak4632 is housed in a space-saving 32-pin qfn package. feature 1. 16-bit delta-sigma mono codec 2. recording function ? 1ch mono input ? 1 st mic amplifier: 0db, 20db, 26db or 32db ? 2 nd amplifier with alc: -8db +27.5db, 0.5db step ? adc performance: s/(n+d): 80db, dr, s/n: 85db 3. playback function ? digital volume: +12db -115db, 0.5db step, mute ? mono line output performance: s/(n+d): 85db, s/n: 93db ? mono speaker-amp - speaker-amp performance: s/(n+d): 60db, s/n: 90db (150mw@ 8 ? ) - btl output - alc (automatic level control) circuit - output power: 400mw @ 8 ? , svdd=3.3v 3.0vrms@svdd=5v ? beep input 4. power management 5. video function ? a composite video input ? gain control (-1.0db +10.5db, 0.5db step) ? low pass filter ? a video-amp for composite video signal(+6db) ? dc direct output or sag compensation output 6. flexible pll mode: ? frequencies: 11.2896mhz, 12mhz, 12.288mhz, 13.5mhz, 24mhz, 27mhz (mcki pin) 1fs (fck pin) 16fs, 32fs or 64fs (bick pin) 7. ext mode: ? frequencies: 256fs, 512fs or 1024fs (mcki pin) 8. sampling rate: ? pll slave mode (fck pin) : 7.35khz ~ 26khz ? pll slave mode (bick pin) : 7.35khz ~ 48khz ? pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz ? pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz ak4632 16-bit ? mono codec with alc & mic/spk/video-amp
asahi kasei [ak4632] ms0396-e-00 2005/06 - 2 - ? ext slave mode: 7.35khz ~ 48khz (256fs), 7.35khz ~ 26khz (512fs), 7.35khz ~ 13khz (1024fs) 9. output master clock frequency: 256fs 10. serial p interface: 3-wire 11. master / slave mode 12. audio interface format: msb first, 2?s compliment ? adc: dsp mode, 16bit msb justified, i 2 s ? dac: dsp mode, 16bit msb justified, 16bit lsb justified, i 2 s 13. ta = -10 70 c 14. power supply ? codec: 2.6 3.6v (typ. 3.3v) ? speaker-amp: 2.6 5.25v (typ. 3.3v/5.0v) ? video-amp: 2.8 5.25v (typ. 3.3v/5.0v) 15. power supply current: 23.5 ma (all power on) 16. package: 32pin qfn 17. register compatible with ak4631 ? block diagram pmmic avdd avss micout ain interface audio mic-amp 0db or 20db or 26db or 32db mic mpi mic power supply hpf adc alc1 (ipga) pmadc fck bick sdto sdti pdn dsp and up csn cclk cdti svdd svss pmdac dvol dac alc2 min mout pmspk spk- amp spp spn alc1m mix aout mcki mcko vcoc pll pmpll pmao daca alc1a dacm beepa control register dvss dvdd vcom beep pmbp vin vout vsag ($" vvdd pmv $-".1 -1' +6db -1db ~ +10.5db step 0.5db figure 1. ak4632 block diagram
asahi kasei [ak4632] ms0396-e-00 2005/06 - 3 - ? ordering guide AK4632VN ? 10 +70 c 32pin qfn (0.5mm pitch) akd4632 evaluation board for ak4632 ? pin layout mout a out beep a in micout mic mpi vcom min svss svdd spp spn mcko mcki dvss v coc a vdd a vss v vdd v in v out v sag pdn dvdd bick fck sdto sdti cdti cclk csn AK4632VN top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 2 3 4 5 6 7 8 18 17 ? compare with ak4632 function ak4631 ak4632 video function no yes package 28pin qfn (5.2mm x 5.2mm) 32pin qfn (5.0mm x 5.0mm) the audio function of the ak4632 is compatible with that of the ak4631. since the register map of audio function is the same as the ak4631?s, the software of the audio function can run on the ak4632 without any change.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 4 - pin/function no. pin name i/o function 1 vcoc o output pin for loop filter of pll circuit this pin should be connected to avss with one resistor and capacitor in series. 2 avdd - analog power supply pin 3 avss - analog ground pin 4 vvdd - video block power supply pin. 5 vin i composite video signal input pin 6 vout o composite video signal driver pin 7 vsag i composite video signal output feedback input pin 8 pdn i power-down mode pin ? h ? : power up, ? l ? : power down reset and initialize the control register. 9 csn i chip select pin 10 cclk i control data clock pin 11 cdti i control data input pin 12 sdti i audio serial data input pin 13 sdto o audio serial data output pin 14 fck i/o frame clock pin 15 bick i/o audio serial data clock pin 16 dvdd - digital power supply pin 17 dvss - digital ground pin 18 mcki i external master clock input pin (internal pull down 25k ? @pdn pin = ? l ? ) 19 mcko o master clock output pin 20 spn o speaker amp negative output pin 21 spp o speaker amp positive output pin 22 svdd - speaker amp power supply pin 23 svss - speaker amp ground pin 24 min i alc2 input pin 25 mout o mono analog output pin 26 aout o mono line output pin 27 beep i beep signal input pin 28 ain i ipga (alc1) input pin 29 micout o microphone analog output pin 30 mic i microphone input pin (mono input) 31 mpi o mic power supply pin for microphone 32 vcom o common voltage output pin. common voltage = 0.45 x avdd bias voltage of adc inputs and dac outputs. note : all input pins except analog input pins (mic, ain, min, beep and vin pins) should not be left floating. note : the exposed pad on the bottom surface of the package must be open.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 5 - ? handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog input mic, ain, beep, min, vsag these pins should be open and each path should be switched off. analog output micout, mpi, aout, mout, spp, spn, vout these pins should be open. digital input mcki, sdti, fck(when m/s bit = ? 0 ? ), bick(when m/s bit = ? 0 ? ) these pins should be connected to dvss. digital output mcko, sdto, fck(when m/s bit = ? 1 ? ), bick(when m/s bit = ? 1 ? ) these pins should be open. absolute maximum ratings (avss, dvss, svss=0v; note 1) parameter symbol min max units power supplies: analog digital speaker-amp video |avss ? dvss| (note 2) |avss ? svss| (note 2) avdd dvdd svdd vvdd ? gnd1 ? gnd2 ? 0.3 ? 0.3 ? 0.3 ? 0.3 - - 6.0 6.0 6.0 6.0 0.3 0.3 v v v v v v input current, any pin except supplies iin - 10 ma analog input voltage(audio) (note 3) vina ? 0.3 avdd+0.3 v analog input voltage(video) (note 4) vinv ? 0.3 vvdd+0.3 v digital input voltage vind ? 0.3 dvdd+0.3 v ambient temperature (powered applied) ta ? 10 70 c storage temperature tstg ? 65 150 c maximum power dissipation (note 5) pd - 700 mw note 1. all voltages with respect to ground. note 2. avss, dvss and svss must be connected to the same analog ground plane. note 3. mic, ain, beep, min pins note 4. vin pin note 5. in case that pcb wiring density is 100%. this power is the ak4632 internal dissipation that does not include power of externally connected speaker. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 6 - recommended operating conditions (avss, dvss, svss=0v; note 1) parameter symbol min typ max units power supplies (note 6) analog digital speaker-amp (note 7) video (note 8) difference avdd dvdd svdd vvdd avdd-dvdd 2.6 2.6 2.6 2.8 or avdd -0.3 3.3 3.3 3.3 / 5.0 3.3 / 5.0 0 3.6 3.6 5.25 5.25 0.3 v v v v v note 1. all voltages with respect to ground note 6. the power up sequence between avdd, dvdd and svdd is not critical. when the power supplies are partially powered off, the ak4632 must be reset by bringing pdn pin ? l ? after these power supplies are powered on again. note 7. svdd = 2.6 3.6v when 8 ? dynamic speaker is connected to the ak4632. if svdd is more than 3.6v when 8 ? dynamic speaker is connected to the ak4632, the output of speaker-amp should be restricted in consideration of maximum power dissipation as the following. spomax : maximum output power of spk-amp[mw] spkmpd : maximum power dissipation of spk-amp[mw] rmin : minimum impedance of speaker[ ? ] vmax : maximum permission output voltage of spk-amp[vrms] spkmpd = 700 ? avdd(max) x 17.5 ? vvdd(max) x 12 ? svdd(max) x 27 a = 2 x sqrt(2) x svdd(max) / b = a x a ? 4 x rmin x spkmpd / 1000 vmax= (a ? sqrt(b)) / 2 spomax = 1000 x vmax x vmax / rmin maximum output power of spk-amp at b < 0 : no limitation maximum output power of spk-amp at b 0: this power should be less than or equal to spomax[mw]. regardless of the condition of b, the distortion of output signal increases, when spk-amp output power exceeds 240mw. note 8. minimum value is higher value between 2.8v and avdd[v]. * akm assumes no responsibility for the usag e beyond the conditions in this datasheet.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 7 - analog chracteristics (ta=25 c; avdd, dvdd, svdd, vvdd=3.3v; avss=dvss=svss=0v; fs=8khz, bick=64fs; signal frequency=1khz; 16bit data; measurement frequency=20hz 3.4khz; ext slave mode; unless otherwise specified) parameter min typ max units mic amplifier input resistance 20 30 40 k ? gain (mgain1-0 bits = ? 00 ? ) (mgain1-0 bits = ? 01 ? ) (mgain1-0 bits = ? 10 ? ) (mgain1-0 bits = ? 11 ? ) - - - - 0 20 26 32 - - - - db db db db mic power supply: mpi pin output voltage (note 9) 2.22 2.47 2.72 v load resistance 2 - - k ? load capacitance - - 30 pf input pga characteristics: input resistance (note 10) 5 10 15 k ? step size 0.05 0.5 0.9 db gain control range ? 8 - +27.5 db adc analog input characteristics: mic ? ipga ? adc, mic gain=20db, ipga=0db, alc1=off resolution - - 16 bits input voltage (mic gain=20db, note 11) 0.168 0.198 0.228 vpp s/(n+d) ( ? 1dbfs) (note 12) 68 80 - db d-range ( ? 60dbfs) 75 85 - db s/n 75 85 - db dac characteristics: resolution - - 16 bits mono line output characteristics: aout pin, dac aout, r l =10k ? output voltage (note 13) 1.78 1.98 2.18 vpp s/(n+d) (0dbfs) (note 12) 73 85 - db d-range (-60dbfs) 83 93 - db s/n 83 93 - db load resistance 10 - - k ? load capacitance - - 30 pf note 9. output voltage is proportional to avdd voltage. vout = 0.75 x avdd (typ) note 10. when ipga gain is changed, this typical value changes between 8k ? and 11k ? . note 11. input voltage is proportional to avdd voltage. vin = 0.06 x avdd (typ) note 12. when a pll reference clock is fck pin in pll slave mode, s/(n+d) is 77db (typ). note 13. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 8 - parameter min typ max units speaker-amp characteristics: spp/spn pins, min ? spp/spn, alc2=off, r l =8 ? , btl, svdd=3.3v output voltage spkg1-0 bits = ? 00 ? (-0.5dbfs) 2.47 3.09 3.71 vpp (note 14) spkg1-0 bits = ? 01 ? (-0.5dbfs) 3.10 4.00 4.80 vpp s/(n+d) at 150mw output 20 60 - db at 240mw output - 50 - db at 400mw output - 20 - db s/n (note 16) 80 90 - db load resistance 8 - - ? load capacitance - - 30 pf speaker-amp characteristics: min ? spp/spn pins, alc2=off, c l =3 f, r serial =10 ? x 2, btl, svdd=5.0v spkg1-0 bits = ? 10 ? - 6.72 - vpp output voltage (note 14) spkg1-0 bits = ? 11 ? 6.80 8.50 10.20 vpp spkg1-0 bits = ? 10 ? - 60 - db s/(n+d) (note 14) (note 15) spkg1-0 bits = ? 11 ? 20 50 - db s/n (note 15) (note 16) 80 80 90 db load impedance (note 17) 50 - - ? load capacitance - - 3 f beep input: beep pin, external input resistance= 20k ? maximum input voltage (note 18) - 1.98 - vpp output voltage (input voltage=0.6vpp) beep ? spp/spn (spkg1-0 bits = ? 00 ? ) 0.74 1.48 2.22 vpp beep ? aout 0.3 0.6 0.9 vpp mono input: min pin maximum input voltage (note 19) - 2.18 - vpp input resistance (note 20) 12 24 36 k ? mono output: mout pin, dac mout output voltage (note 21) 1.78 1.98 2.18 vpp load resistance 10 - - k ? load capacitance - - 30 pf note 14. the full scale of input signal of min pin is 1.98vpp. note 15. in case of measuring between spp pin and spn pin directly. note 16. there are no relations with the setup of spkg1-0 bits, and it is the same value. note 17. load impedance is total impedance of series resist ance and piezo speaker impedance at 1khz in figure 35. load capacitance is capacitance of piezo speaker. when piezo speaker is used, 10 ? or more series resistors should be connected at both spp and spn pins, respectively. note 18. the maximum input voltage of the beep is proportional to avdd voltage and external input resistance(rin). vout = 0.6 x avdd x rin/20k ? (max). note 19. maximum input voltage is proportional to avdd voltage. vin = 0.66 x avdd (max) note 20. when alc2 gain is changed, this typical value changes between 22k ? and 26k ? . note 21. output voltage is proportional to avdd voltage. vout = 0.6 x avdd (typ)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 9 - parameter min typ max units y input characteristics: maximum input voltage (note 22) - 1.2 - vpp pull down current - 2.0 - a v output characteristics: output gain vin=100khz (gca=0db) 5.0 6.0 7.0 db maximum output at dc output 2.4 2.52 - vpp voltage at sag compensation output 100 f+2.2 uf, vvdd 3.135 v - 2.4 - vpp at sag compensation output 47 f+1.0uf, vvdd 3.135 v - 2.4 - vpp clamp voltage at dc output - 0.15 - v s/n bw=100kh 6mhz - 66 - db secondary distortion vin=3.58mhz, 1.0vpp(sin wave) (note 23) - -45 - db load resistance 140 150 - ? load capacitance c1(see figure 2) c2(see figure 2) (note 24) - - - - 15 400 pf pf lpf frequency response response at 6.75mhz -3.0 -0.5 - db input=1.26vpp, sin wave response at 27mhz - -30 -20 db (0db at 100khz) group delay |gd3mhz ? gd6mhz| - 10 100 nsec gca characteristics: step size gca = -1.0db +10.5db 0.1 0.5 0.9 db power supplies power up (pdn = ? h ? ) all circuit power-up: (note 25) avdd+dvdd fs=8khz - 9 - ma fs=48khz - 11.5 17.5 ma svdd: speaker-amp normal operation (spps bit = ? 1 ? , no output) svdd=3.3v - 7 - ma svdd=5.0v - 9 27 ma vvdd (note 26) vvdd=3.3v - 7.5 - ma vvdd=5.0v - 8 12 ma power down (pdn = ? l ? ) (note 27) avdd+dvdd+svdd+vvdd - 10 100 a note 22. input voltage doesn?t depend on vvdd. note 23. in the case of using sag compensation circuit with 47 f+ 1.0uf and sagc1-0 bits = ? 10 ? note 24. r1 and c2 compose of low pass filter(lpf) in figure 2. the cut off frequency of lpf is 10.6mhz at c2 = 400pf. video signal output 75 ohm 75 oh m c2 r1 r2 c1 figure 2. load capacitance c1 and c2
asahi kasei [ak4632] ms0396-e-00 2005/06 - 10 - note 25. pll master mode (mcki=12.288mhz) and pmv=pmmic = pmadc = pmdac = pmspk = pmvcm = pmpll = mcko = pmao = pmbp = mpwr = m/s = ? 1 ? . and output current from mpi pin is 0ma. when the ak4632 is ext mode (pmpll = mcko = m/s = ? 0 ? ), ? avdd+dvdd ? is typically 7ma@fs=8khz, 9.5ma@fs=48khz). note 26. this is the case of sagc bits = ? 00 ? and no load resistance and capacitance. when sagc bits = ? 10 ? and black signal is output, this current is typ.8ma. in the case of dc output, this current increases by dc voltage / 150 ? . dc output voltage is 0v at pmv bit = ? 0 ? , and then dc current doesn?t flow. when any signal isn?t input at using sag compensation circuit, pmv bit should be set to ? 0 ? . note 27. mcki pin is fixed to dvss and all digital inputs pins except mcki pin are fixed to dvss or dvss. filter chracteristics (ta = 25 c; avdd, dvdd = 2.6 3.6v; svdd =2.6 5.25v; vvdd =2.8 5.25v; fs=8khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 28) 0.16db ? 0.66db ? 1.1db ? 6.9db pb 0 - - - - 3.5 3.6 4.0 3.0 - - - khz khz khz khz stopband (note 28) sb 4.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 73 - - db group delay (note 29) gd - 17.1 - 1/fs group delay distortion ? gd - 0 - s adc digital filter (hpf): frequency response (note 28) ? 3.0db ? 0.5db ? 0.1db fr - - - 0.62 1.81 3.99 - - - hz hz hz dac digital filter: passband (note 28) 0.1db ? 0.7db ? 6.0db pb 0 - - - 3.6 4.0 3.6 - - khz khz stopband (note 28) sb 4.6 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 59 - - db group delay (note 29) gd - 16.8 - 1/fs dac digital filter + analog filter: frequency response: 0 3.4khz fr - 1.0 - db note 28. the passband and stopband frequencies are proportional to fs (system sampling rate). for example, adc is pb=0.45*fs (@-1.1db). a reference of frequency response is 1khz. note 29. the calculated delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16-bit data of a channel from the input register to the output register of the adc. this time includes the group delay of the hpf. for the dac, this time is from setting the 16-bit data of a channel from the input register to the output of analog signal. dc chracteristics (ta = 25 c; avdd, dvdd = 2.6 3.6v; svdd =2.6 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd - - - - 30%dvdd v v high-level output voltage (iout= ? 80 a) low-level output voltage (iout= 80 a) voh vol dvdd ? 0.4 - - - - 0.4 v v input leakage current iin - - 10 a
asahi kasei [ak4632] ms0396-e-00 2005/06 - 11 - switing characteristics (ta = 25 c; avdd, dvdd = 2.6 3.6v; svdd =2.6 5.25v ; vvdd =2.8 5.25v; c l =20pf) parameter symbol min typ max units pll master mode (pll reference clock = mcki pin) (figure 3) mcki input: frequency pulse width low pulse width high fclk tclkl tclkh 11.2896 0.4/fclk 0.4/fclk - - - 27.0 - - mhz ns ns mcko output: frequency duty cycle except fs=29.4khz, 32khz fs=29.4khz, 32khz (note 30) fmck dmck dmck - 40 - 256 x ffck 50 33 - 60 - khz % % fck output: frequency duty cycle ffck dfck 8 - - 50 48 - khz % bick: period (bcko1-0 = ? 00 ? ) (bcko1-0 = ? 01 ? ) (bcko1-0 = ? 10 ? ) duty cycle tbck tbck tbck dbck - - - - 1/16ffck 1/32ffck 1/64ffck 50 - - - - ns ns ns % audio interface timing dsp mode: (figure 4, figure 5) fck ? ? to bick ? ? (note 31) fck ? ? to bick ? ? (note 32) bick ? ? to sdto (bckp = ? 0 ? ) bick ? ? to sdto (bckp = ? 1 ? ) sdti hold time sdti setup time tdbf tdbf tbsd tbsd tsdh tsds 0.5 x tbck -40 0.5 x tbck -40 -70 -70 50 50 0.5 x tbck 0.5 x tbck - - - - 0.5 x tbck + 40 0.5 x tbck +40 70 70 - - ns ns ns ns ns ns except dsp mode: (figure 6) bick ? ? to fck edge fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tbfck tfsd tbsd tsdh tsds -40 -70 -70 50 50 - - - - - 40 70 70 - - ns ns ns ns ns
asahi kasei [ak4632] ms0396-e-00 2005/06 - 12 - parameter symbol min typ max units pll slave mode (pll reference clock: fck pin) (figure 7, figure 8) fck: frequency dsp mode: pulse width high except dsp mode: duty cycle ffck tfckh duty 7.35 tbck-60 45 8 - - 26 1/ffck-tbfck 55 khz ns % bick: period pulse width low pulse width high tbck tbckl tbckh 1/64ffck 240 240 - - - 1/16ffck - - ns ns ns pll slave mode (pll reference clock: bick pin) (figure 7, figure 8) fck: frequency dsp mode: pulse width high except dsp mode: duty cycle ffck tfckh duty 7.35 tbck-60 45 8 - - 48 1/ffck-tbfck 55 khz ns % bick: period (pll3-0 = ? 0001 ? ) (pll3-0 = ? 0010 ? ) (pll3-0 = ? 0011 ? ) pulse width low pulse width high tbck tbck tbck tbckl tbckh - - - 0.4 x tbck 0.4 x tbck 1/16ffck 1/32ffck 1/64ffck - - - - - - - ns ns ns ns ns pll slave mode (pll reference clock: mcki pin) ( figure 9) mcki input: frequency pulse width low pulse width high fclk fclkl fclkh 11.2896 0.4/fclk 0.4/fclk - - - 27.0 - - mhz ns ns mcko output: frequency duty cycle except fs=29.4khz, 32khz fs=29.4khz, 32khz (note 30) fmck dmck dmck - 40 - 256 x ffck 50 33 - 60 - khz % % fck: frequency dsp mode: pulse width high except dsp mode: duty cycle ffck tfckh duty 8 tbck-60 45 - - - 48 1/ffck-tbfck 55 khz ns % bick: period pulse width low pulse width high tbck tbckl tbckh 1/64ffck 0.4 x tbck 0.4 x tbck - - - 1/16ffck - - ns ns ns audio interface timing dsp mode: (figure 10,figure 11) fck ? ? to bick ? ? (note 31) fck ? ? to bick ? ? (note 32) bick ? ? to fck ? ? (note 31) bick ? ? to fck ? ? (note 32) bick ? ? to sdto (bckp = ? 0 ? ) bick ? ? to sdto (bckp = ? 1 ? ) sdti hold time sdti setup time tfckb tfckb tbfck tbfck tbsd tbsd tsdh tsds 0.4 x tbck 0.4 x tbck 0.4 x tbck 0.4 x tbck - - 50 50 - - - - - - - - - - - - 80 80 - - ns ns ns ns ns ns ns ns except dsp mode: (figure 13) fck edge to bick ? ? (note 33) bick ? ? to fck edge (note 33) fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tfckb tbfck tfsd tbsd tsdh tsds 50 50 - - 50 50 - - - - - - - - 80 80 - - ns ns ns ns ns ns
asahi kasei [ak4632] ms0396-e-00 2005/06 - 13 - parameter symbol min typ max units ext slave mode (figure 12) mcki frequency: 256fs 512fs 1024fs pulse width low pulse width high fclk fclk fclk tclkl tclkh 1.8816 3.7632 7.5264 0.4/fclk 0.4/fclk 2.048 4.096 8.192 - - 12.288 13.312 13.312 - - mhz mhz mhz ns ns fck frequency (mcki = 256fs) (mcki = 512fs) (mcki = 1024fs) duty cycle ffck ffck ffck duty 7.35 7.35 7.35 45 8 8 8 - 48 26 13 55 khz khz % bick period bick pulse width low pulse width high tbck tbckl tbckh 312.5 130 130 - - - - - - ns ns ns audio interface timing (figure 13) fck edge to bick ? ? (note 33) bick ? ? to fck edge (note 33) fck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tfckb tbfck tfsd tbsd tsdh tsds 50 50 - - 50 50 - - - - - - - - 80 80 - - ns ns ns ns ns ns note 30. duty cycle = (the width of ? l ? ) / (the period of clock) 100 note 31. msbs, bckp bits = ? 00 ? or ? 11 ? note 32. msbs, bckp bits = ? 01 ? or ? 10 ? note 33. bick rising edge must not occur at the same time as fck edge. parameter symbol min typ max units control interface timing: cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ? h ? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 150 50 - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns reset timing pdn pulse width (note 34) pmadc ? ? to sdto valid (note 35) tpd tpdv 150 - - 1059 - - ns 1/fs note 34. the ak4632 can be reset by the pdn pin = ? l ? note 35. this is the count of fck ? ? from the pmadc = ? 1 ? .
asahi kasei [ak4632] ms0396-e-00 2005/06 - 14 - ? timing diagram fck 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckoh tmckol 50%dvdd 1/ffck dfck dfck 50%dvdd dmck = tmckol x fmck x 100 figure 3. clock timing (pll master mode) fck bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih dbck tdbf 50%dvdd tbck msb msb bick 50%dvdd (bckp = "0") (bckp = "1") figure 4. audio interface timing (pll master mode & dsp mode: msbs = ? 0 ? )
asahi kasei [ak4632] ms0396-e-00 2005/06 - 15 - fck bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih dbck tdbf 50%dvdd tbck msb bick 50%dvdd (bckp = "1") (bckp = "0") msb figure 5. audio interface timing (pll master mode & dsp mode: msbs = ? 1 ? ) fck 50%dvdd bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tbfck dbck tfsd figure 6. audio interface timing (pll master mode & except dsp mode)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 16 - 1/ffck fck vih tfckh vil tbck bick tbckh tbckl vih vil tbfck bick vih vil (bckp = "0") (bckp = "1") figure 7. clock timing (pll slave mode ; pll reference clock = fck or bick pin & dsp mode; msbs = 0) 1/ffck fck vih tfckh vil tbck bick tbckh tbckl vih vil tbfck bick vih vil (bckp = "1") (bckp = "0") figure 8. clock timing (pll slave mode; pll reference clock = fck or bick pin & dsp mode; msbs = 1)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 17 - 1/fclk mcki tclkh tclkl vih vil 1/ffck fck vih vil tbck bick tbckh tbckl vih vil tfckh tfckl 1/fmck mcko 50%dvdd tmckoh tmckol dmck = tmckol x fmck x 100 figure 9. clock timing (pll slave mode; pll reference clock = mcki pin & except dsp mode)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 18 - fck bick sdto 50%dvdd tbsd tsds sdti vil tsdh vih tfckb tfckh msb msb vil vih vil vih bick vil vih (bckp = "0") (bckp = "1") figure 10. audio interface timing (pll slave mode & dsp mode; msbs = 0) fck bick sdto 50%dvdd tbsd tsds sdti vil tsdh vih tfckb tfckh msb msb vil vih vil vih bick vil vih (bckp = "1") (bckp = "0") figure 11. audio interface timing (pll slave mode, dsp mode; msbs = 1)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 19 - 1/fclk mcki tclkh tclkl vih vil 1/ffck fck vih vil tbck bick tbckh tbckl vih vil tfckh tfckl figure 12. clock timing (ext slave mode) fck vih vil tbfck bick vih vil tfsd sdto 50%dvdd tfckb tbsd tsds sdti vil tsdh vih msb figure 13. audio interface timing (pll, ext slave mode & except dsp mode)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 20 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck figure 14. write command input timing csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 figure 15. write data input timing csn vih vil tpdv sdto 50%dvdd figure 16. power down & reset timing 1 tpd pdn vil figure 17. power down & reset timing 2
asahi kasei [ak4632] ms0396-e-00 2005/06 - 21 - operation overview ? system clock there are the following four clock modes to interface with external devices. (see table 1 and table 2) mode pmpll bit m/s bit pll3-0 bit mckpd bit figure pll master mode 1 1 see table 4 0 figure 19 pll slave mode 1 (pll reference clock: mcki pin) 1 0 see table 4 0 figure 20 pll slave mode 2 (pll reference clock: fck or bick pin) 1 0 see table 4 1 figure 21 ext slave mode 0 0 x 0 figure 22 invalid state (note 36) 0 1 x x - table 1. clock mode setting (x: don?t care) note 36. if this mode is selected, the invalid clocks are output from mcko, fck and bick pins. mode mcko bit mcko pin mcki pin bick pin fck pin 0 ? l ? output pll master mode 1 256fs output master clock input for pll (note 37) 16fs/32fs/64fs output 1fs output 0 ? l ? output pll slave mode 1 (pll reference clock: mcki pin) 1 256fs output master clock input for pll (note 37) 16fs/32fs/64fs input 1fs input pll slave mode 2 (pll reference clock: fck or bick pin) 0 ? l ? output gnd 16fs/32fs/64fs input 1fs input ext slave mode 0 ? l ? output 256fs/ 512fs/ 1024fs input 32fs input 1fs input note 37. 11.2896mhz/12mhz/12.288mhz/13.5mhz/24mhz/27mhz table 2. clock pins state in clock mode [pull-down resistor of mcki pin] when the master clock is input, mckpd bit should be ? 0 ? . when the mcki pin is floating, the pin should be pulled-down by internal 25k ? resistor at mckpd bit = ? 1 ? (default). mcki ak4632 25k ? mckpd bit ="0" figure 18. pull-down resistor of mcki pin
asahi kasei [ak4632] ms0396-e-00 2005/06 - 22 - ? master mode/slave mode the m/s bit selects either mast er or slave modes. m/s bit = ? 1 ? selects master mode and ? 0 ? selects slave mode. when the ak4632 is power-down mode (pdn pin = ? l ? ) and exits reset state, the ak4632 is slave mode. after exiting reset state, the ak4632 goes master mode by changing m/s bit = ? 1 ? . when the ak4632 is used by master mode, fck and bick pins are a floating state until m/s bit becomes ? 1 ? . fck and bick pins of the ak4632 should be pulled-down or pulled-up by about 100k ? resistor externally to avoid the floating state. m/s bit mode 0 slave mode default 1 master mode table 3. select master/salve mode ? pll mode when pmpll bit is ? 1 ? , a fully integrated analog phase locked loop (pll) generates a clock that is selected by the pll3-0 and fs3-0 bits. the pll lock time is shown in table 4, whenever the ak4632 is supplied to a stable clocks after pll is powered-up (pmpll bit = ? 0 ? ? 1 ? ) or sampling frequency changes. 1) setting of pll mode r and c of vcoc pin mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency r[ ? ] c[f] pll lock time (max) 0 0 0 0 0 fck pin 1fs 6.8k 220n 160ms default 1 0 0 0 1 bick pin 16fs 10k 4.7n 2ms 2 0 0 1 0 bick pin 32fs 10k 4.7n 2ms 3 0 0 1 1 bick pin 64fs 10k 4.7n 2ms 4 0 1 0 0 mcki pin 11.2896mhz 10k 4.7n 40ms 5 0 1 0 1 mcki pin 12.288mhz 10k 4.7n 40ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 40ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 40ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 40ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 40ms others others n/a table 4. setting of pll mode (*fs: sampling frequency) 2) setting of sampling frequency in pll mode. when pll2 bit is ? 1 ? (pll reference clock input is mcki pin), the sampling frequency is selected by fs2-0 bits as defined in table 5. mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz default 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 5 0 1 0 1 11.025khz 6 0 1 1 0 14.7khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 15 1 1 1 1 44.1khz others others n/a table 5. setting of sampling frequency at pll2 bit = ? 1 ? and pmpll bit = ? 1 ?
asahi kasei [ak4632] ms0396-e-00 2005/06 - 23 - when pll2 bit is ? 0 ? (pll reference clock input is fck or bick pin), the sampling frequency is selected by fs3, fs1-0 bits. (see table 6) mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 don?t care 0 0 7.35khz fs 8khz default 1 0 don?t care 0 1 8khz < fs 12khz 2 0 don?t care 1 0 12khz < fs 16khz 3 0 don?t care 1 1 16khz < fs 24khz 6 1 don?t care 1 0 24khz < fs 32khz 7 1 don?t care 1 1 32khz < fs 48khz others others n/a table 6. setting of sampling frequency at pll2 bit = ? 0 ? and pmpll bit = ? 1 ? ? pll unlock state 1) pll master mode (pmpll bit = ? 1 ? , m/s bit = ? 1 ? ) in this mode, irregular frequency clocks are output from fck, bick and mcko pins after pmpll bit = ? 0 ? ? ? 1 ? or sampling frequency is changed. after that pll is unlocked, bick and fck pins output ? l ? for a moment, and invalid frequency clock is output from mcko pin at mcko bit = ? 1 ? . if mcko bit is ? 0 ? , mcko pin is output to ? l ? . (see table 7) after the pll is locked, a first period of fck and bick may be invalid clock, but these clocks return to normal state after a period of 1/fs. mcko pin pll state mcko bit = ? 0 ? mcko bit = ? 1 ? bick pin fck pin after that pmpll bit ? 0 ? ? ? 1 ? ? l ? output invalid invalid invalid pll unlock ? l ? output invalid ? l ? output ? l ? output pll lock ? l ? output 256fs output see table 9 1fs output table 7. clock operation at pll master mode (pmpll bit = ? 1 ? , m/s bit = ? 1 ? ) 2) pll slave mode (pmpll bit = ? 1 ? , m/s bit = ? 0 ? ) in this mode, an invalid clock is output from mcko pin after pmpll bit = ? 0 ? ? ? 1 ? or sampling frequency is changed. after that, 256fs is output from mcko pin when pll is locked. adc and dac output invalid data when the pll is unlocked. for dac, the output signal should be muted by writing ? 0 ? to daca and dacm bits in addr=02h. mcko pin pll state mcko bit = ? 0 ? mcko bit = ? 1 ? after that pmpll bit ? 0 ? ? ? 1 ? ? l ? output invalid pll unlock ? l ? output invalid pll lock ? l ? output 256fs output table 8. clock operation at pll slave mode (pmpll bit = ? 1 ? , m/s bit = ? 0 ? )
asahi kasei [ak4632] ms0396-e-00 2005/06 - 24 - ? pll master mode (pmpll bi t = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz , 12.288mhz, 13.5mhz, 24mhz or 27mhz) is input to mcki pin, the mcko, bick and fck clocks are generated by an internal pll circuit. the mcko output frequency is fixed to 256fs, the output is enabled by mcko bit. the bick is selected among 16fs, 32fs or 64fs, by bcko1-0 bits. (see table 9) when bick output frequency is 16fs, the audio in terface format supports only mode 0 (dsp mode). ak4632 dsp or p mcko bick fck sdto sdti bclk fck sdti sdto mcki 1fs 16fs, 32fs, 64fs 256fs 11.2896m hz, 12m hz, 12.288mhz 13.5m hz, 24mhz, 27m hz mclk figure 19. pll master mode mode bcko1 bcko0 bick output frequency 0 0 0 16fs default 1 0 1 32fs 2 1 0 64fs 3 1 1 n/a table 9. bick output frequency at master mode
asahi kasei [ak4632] ms0396-e-00 2005/06 - 25 - ? pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to mcki, bick or fck pin. the required clock to the ak4632 is generated by an internal pll circuit. input frequency is selected by pll3-0 bits. when bick input frequency is 16fs, the audio interface format supports only mode 0 (dsp mode). a) pll reference cloc k: bick or fck pin in the case of using bick as pll reference clock, the sampling frequency corresponds to 7.35khz to 48khz by changing fs3-0 bits. in the case of using fck, the samp ling frequency corresponds to 7.35khz to 26khz. (seetable 6) ak4632 dsp or p mcki bick fck sdto sdti bclk fck sdti sdto mcko 1fs 16fs, 32fs, 64fs figure 20. pll slave mode 1 (pll reference clock: fck or bick pin) b) pll reference clock: mcki pin bick and fck inputs should be synchronized with mcko output. the phase between mcko and fck dose not matter. sampling frequency can be selected by fs3-0 bits. (see table 5) ak4632 dsp or p mcko bick fck sdto sdti bclk fck sdti sdto mcki 1fs 16fs, 32fs, 64fs 256fs 11.2896m hz, 12m hz, 12.288mhz 13.5m hz, 24mhz, 27m hz mclk figure 21. pll slave mode 2 (pll reference clock: mcki pin) the external clocks (mcki, bick and fck) should always be present whenever the adc or dac is in operation (pmadc bit = ? 1 ? or pmdac bit = ? 1 ? ). if these clocks are not provided, the ak4632 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshe d logic internally. if the external clocks are not present, the adc and dac should be in the power-down mode (pmadc bit =pmdac bit = ? 0 ? ).
asahi kasei [ak4632] ms0396-e-00 2005/06 - 26 - ? ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ? 0 ? , the ak4632 becomes ext mode. master clock is input from mcki pin, the internal pll circuit is not operated. this mode is compatible with i/f of the normal audio codec. the clocks required to operate are mcki (256fs, 512fs or 1024fs), fck (fs) and bick (32fs ). the master clock (mcki) should be synchronized with fck. the phase between these clocks does not matter. the input frequency of mcki is selected by fs3-0 bits. (see table 10) mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz fs 48khz default 1 don?t care 0 1 1024fs 7.35khz < fs 13khz 2 don?t care 1 0 256fs 7.35khz < fs 48khz 3 don?t care 1 1 512fs 7.35khz < fs 26khz table 10. mcki frequency at ext slave mode (pmpll bit = ? 0 ? , m/s bit = ? 0 ? ) external slave mode does not support mode 0 (dsp mode) of audio interface format. the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. when the out-of-band noise can be improved by using higher fr equency of the master clock. the s/n of the dac output through aout amp at fs=8khz is shown in table 11. mcki s/n (fs=8khz, 20khzlpf + a-weight) 256fs 83db 512fs 93db 1024fs 93db table 11. relationship between mcki and s/n of aout the external clocks (mcki, bick and fck) should always be present whenever the adc or dac is in operation (pmadc bit = ? 1 ? or pmdac bit = ? 1 ? ). if these clocks are not provided, the ak4632 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshe d logic internally. if the external clocks are not present, the adc and dac should be in the power-down mode (pmadc bit = pmdac bit = ? 0 ? ). ak4632 dsp or p mcki bick fck sdto sdti bclk fck sdti sdto mcko 1fs 32fs, 64fs mclk 256fs, 512fs or 1024fs figure 22. ext slave mode
asahi kasei [ak4632] ms0396-e-00 2005/06 - 27 - ? audio interface format four types of data formats are available and are selected by setting the dif1-0 bits. (see table 12) in all modes, the serial data is msb first, 2?s complement format. audio interface formats can be used in both master and slave modes. fck and bick are output from ak4632 in master mode, but must be input to ak4632 in slave mode. in mode 1-3, the sdto is clocked out on the falling edge of bick and the sdti is latched on the rising edge. mode dif1 dif0 sdto (adc) sdti (dac) bick figure 0 0 0 dsp mode dsp mode 16fs see table 13 1 0 1 msb justified msb justified 32fs figure 27 2 1 0 msb justified msb justified 32fs figure 28 default 3 1 1 i 2 s compatible i 2 s compatible 32fs figure 29 table 12. audio interface format in mode0 (dsp mode), the audio i/f timing is changed by bckp and msbs bits. when bckp bit is ? 0 ? , sdto data is output by rising edge of bick, sdti data is latched by falling edge of bick. when bckp bit is ? 1 ? , sdto data is output by falling edge of bick, sdti data is latched by rising edge of bick. msb data position of sdto and sdti can be shifted by msbs bit. the shifted period is a half of bick. msbs bit bckp bit audio interface format 0 0 figure 23 default 0 1 figure 24 1 0 figure 25 1 1 figure 26 table 13. audio interface format in mode 0 if 16-bit data that adc outputs is converted to 8-bit data by removing lsb 8-bit, ? ? 1 ? at 16bit data is converted to ? ? 1 ? at 8-bit data. and when the dac playbacks this 8-bit data, ? ? 1 ? at 8-bit data will be converted to ? ? 256 ? at 16-bit data and this is a large offset. this offset can be removed by adding the offset of ? 128 ? to 16-bit data before converting to 8-bit data. ? system reset upon power-up, reset the ak4632 by bringing the pdn pin = ? l ? . this ensures that all intern al registers reset to their initial values. the adc enters an initialization cycle that starts when the pmadc bit is changed from ? 0 ? to ? 1 ? . the initialization cycle time is 1059/fs, or 133ms@fs=8khz. during the initialization cycle, the adc digital data outputs of both channels are forced to a 2's compliment, ? 0 ? . the adc output reflects the analog input signal after the initialization cycle is complete. the dac does not require an initialization cycle.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 28 - fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 8 8 7 1 43 10 13 2 6 0 15 4 876 0 3 2 1 5 13 10 15 2 14 14 2 0 15 5 8 7 1 432 6 0 15 4 76 0 3 2 1 515 14 14 sdti(i) bick ( 32fs ) sdto(o) 15 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 8 2 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 23. mode 0 timing (bckp = ? 0 ? , msbs = ? 0 ? ) fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 8 8 7 1 43 10 13 2 6 0 15 4 876 0 3 2 1 5 13 10 15 2 14 14 2 0 15 5 8 7 1 432 6 0 15 4 76 0 3 2 1 515 14 14 sdti(i) bick ( 32fs ) sdto(o) 15 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 8 2 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 24. mode 0 timing (bckp = ? 1 ? , msbs = ? 0 ? )
asahi kasei [ak4632] ms0396-e-00 2005/06 - 29 - fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 8 8 7 1 43 10 13 2 6 0 15 4 876 0 3 2 1 5 13 10 15 2 14 14 2 0 15 5 8 7 1 432 6 0 15 4 76 0 3 2 1 515 14 14 sdti(i) bick ( 32fs ) sdto(o) 15 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 8 2 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 25. mode 0 timing (bckp = ? 0 ? , msbs = ? 1 ? ) fck bick ( 16fs ) sdto(o) 15 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 0 15 5 8 8 7 1 43 10 13 2 6 0 15 4 876 0 3 2 1 5 13 10 15 2 14 14 2 0 15 5 8 7 1 432 6 0 15 4 76 0 3 2 1 515 14 14 sdti(i) bick ( 32fs ) sdto(o) 15 0 1 8 14 15 17 18 30 31 0 1 8 8 9 11 12 30 31 0 15 8 2 1 16 29 0 15 821 0 13 10 15:msb, 0:lsb 1/fs 2 14 14 2 15 2 1 0 15 8210 14 14 sdti(i) 1/fs don?t care don?t care figure 26. mode 0 timing (bckp = ? 1 ? , msbs = ? 1 ? )
asahi kasei [ak4632] ms0396-e-00 2005/06 - 30 - fck bick(32fs) sdto(o) 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 8 7 6 0 32 11 1 4 1 5 14 11 15 bick(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 14 15 17 18 31 0 15 1 14 0 15 sdti(i) 10 15 14 15:msb, 0:lsb data 1/fs don?t care 2 1 13 don?t care 16 16 3 3 13 3 15 14 4 7 6 0 321 5 15 13 sdti(i) don?t care figure 27. mode 1 timing fck bick(32fs) sdto(o) 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 8 7 6 0 32 11 1 4 1 5 14 11 15 13 bick(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 14 14 15 17 18 31 0 15 1 14 0 15 sdti(i) 15:msb, 0:lsb data 1/fs don?t care 2 1 13 don?t care 16 16 3 13 15 14 2 1 13 0 15 sdti(i) 15 14 4 8 7 6 0 321 5 15 don?t care figure 28. mode 2 timing
asahi kasei [ak4632] ms0396-e-00 2005/06 - 31 - fck bick(32fs) sdto(o) 0 1 2 4 9 10 12 13 15 0 1 2 4 9 10 12 13 15 0 1 15 5 13 7 7 1 43 11 1 4 2 6 0 14 11 13 bick(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 4 14 15 17 18 31 0 1 15 0 sdti(i) 15:msb, 0:lsb data 1/fs don?t care 2 1 14 don?t care 16 16 3 13 15 2 1 14 0 14 3 3 4 sdti(i) 15 5 13 7 1 432 6 0 14 figure 29. mode 3 timing ? digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 1.25hz (@fs=8khz) and scales with sampling rate (fs). ? mic gain amplifier the ak4632 has a gain amplifier for microphone input. this gain is 0db, +20db, +26db or +32db, selected by the mgain1-0 bit. the typical input impedance is 30k ? . mgain1 bit mgain0 bit input gain 0 0 0db 0 1 +20db default 1 0 +26db 1 1 +32db table 14. input gain ? mic power the mpi pin supplies power for the microphone. this output voltage is typically 0.75 x avdd and the load resistance is minimum 2k ? . no capacitor must not be connected directly to mpi pin. (see figure 30) mpi pin 2k ? figure 30. mic block circuit
asahi kasei [ak4632] ms0396-e-00 2005/06 - 32 - ? manual mode the ak4632 becomes a manual mode at alc1 bit = ? 0 ? . this mode is used in the case shown below. 1. after exiting reset state, set up the registers for the alc1 operation (ztm1-0, lmth and etc) 2. when the registers for the alc1 operation (limiter period, recovery period and etc) are changed. for example; when the change of the sampling frequency. 3. when ipga is used as a manual volume. when ipga6-0 bits are written at manual mode, the counter for zero cross time out is reset and restart. the ipga6-0 bits value are reflected to ipga at zero cross or zero cross time out. the time of zero cross time out is set by ztm1-0 bits. when writing to ipga6-0 bits continually, the control register should be written by an interval of more than zero crossing timeout. ? mic-alc operation the alc (automatic level control) of mic input is done by alc1 block when alc1 bit is ? 1 ? . [1] alc1 limiter operation when the alc1 limiter is enabled, and ipga output exceeds the alc1 limiter detection level (lmth), the ipga value is attenuated by the amount defined in the alc1 limiter att step (lmat1-0 bits) automatically. when the zelm bit = ? 1 ? , the timeout period is set by the ltm1-0 bits. the operation for attenuation is done continuously until the input signal level becomes lmth or less. if the alc1 bit does not change into ? 0 ? after completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds lmth. when the zelm bit = ? 0 ? , the timeout period is set by the ztm1-0 bits. this enables the zero-crossing attenuation function so that the ipga value is attenuated at the zero-detect points of the waveform. [2] alc1 recovery operation the alc1 recovery refers to the amount of time that the ak4632 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. the alc1 recovery operation uses the wtm1-0 bits to define the wait period used after completing an alc1 limiter operation. if the input signal does not exceed the ? alc1 recovery waiting counter reset level ? , the alc1 recovery operation starts. the ipga value increases automatically during this operation up to the reference level (ref6-0 bits). the alc1 recovery operation is done at a period set by the wtm1-0 bits. zero crossing is detected during wtm1-0 period, the alc1 recovery operation waits wtm1-0 period and the next recovery operation starts. during the alc1 recovery operation, when input signal level exceeds the alc1 limiter detection level (lmth), the alc1 recovery operation changes immediately into an alc1 limiter operation. in the case of ? (recovery waiting counter reset level) ipga output level < limiter detection level ? during the alc1 recovery operation, the wait timer for the alc1 recove ry operation is reset. therefore, in the case of ? (recovery waiting counter reset level) > ipga output level ? , the wait timer for the alc1 recovery operation starts. the alc1 operation corresponds to the impulse noise. when the impulse noise is input, the alc1 recovery operation becomes faster than a normal recovery operation.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 33 - [3] example of alc1 operation table 15 shows the example of the alc1 setting. in cas e of this example, alc1 operation starts from 0db. fs=8khz fs=16khz register name comment data operation data operation lmth limiter detection level 1 -4dbfs 1 -4dbfs ltm1-0 limiter ope ration period at zelm = 1 00 don?t use 00 don?t use zelm limiter zero crossing dete ction 0 enable 0 enable ztm1-0 zero crossing timeout period 00 16ms 01 16ms wtm1-0 recovery waiting period *wtm1-0 bits should be the same data as ztm1-0 bits 00 16ms 01 16ms ref6-0 maximum gain at recovery operation 47h +27.5db 47h +27.5db ipga6-0 ipga gain at the start of alc1 operation 10h 0db 10h 0db lmat1-0 limiter att step 00 1 step 00 1 step ratt recovery gain step 0 1 step 0 1 step alc1 alc1 enable bit 1 enable 1 enable table 15. examples of the alc1 setting the following registers should not be changed during the alc1 operation. these bits should be changed, after the alc1 operation is finished by alc1 bit = ? 0 ? or pmmic bit = ? 0 ? . ? ltm1-0, lmth, lmat1-0, wtm1-0, ztm1-0, ratt, ref6-0, zelm bits when setting ipga gain at the start of alc1 operation, ipga6-0 bits should be set while pmmic bit is ? 1 ? and alc1 bit is ? 0 ? . when pmmic bit = ? 1 ? , ipga6-0 bits value aren?t reflected to ipga. when alc1 bit is changed from ? 1 ? to ? 0 ? , ipga holds the last gain value set automatically by alc1 operation. manual mode * the value of ipga should be the same or smaller than ref?s wr (ztm1-0, wtm1-0, ltm1-0) wr (ref6-0) wr (ipga6-0) alc1 o p eration wr (alc1= ?1?, lmat1-0, ratt, lmth, zelm) example: limiter = zero crossing enable recovery cycle = 16ms @ fs= 8khz limiter and recovery step = 1 maximum gain = +27.5db limiter detection level = -4dbfs alc2 bit = ?1? (default) (1) addr=06h, data=00h (2) addr=08h, data=47h (4) addr=07h, data=61h (3) addr=09h, data=10h note : wr : write figure 31. registers set-up sequence at the alc1 operation
asahi kasei [ak4632] ms0396-e-00 2005/06 - 34 - ? digital output volume the ak4632 has a digital output volume (256 levels, 0.5db step, mute). the volume can be set by the dvol7-0 bits. the volume is included in front of a dac block, a input data of dac is changed from +12 to ?115db with mute. this volume has a soft transition function. it takes 1061/fs or 256/fs from 00h to ffh. dvol7-0 gain 00h +12.0db 01h +11.5db 02h +11.0db ? ? 18h 0db default ? ? fdh ? 114.5db feh ? 115.0db ffh mute ( ? ) table 16. digital output volume code table the transition time from 00h to ffh of dvol7-0 bits dvtm bit transition time fs=8khz fs=22.05khz 0 1061/fs 133msec 48msec 1 256/fs 32msec 12msec table 17.setting of transition time ? beep input when the pmbp bit is set to ? 1 ? , the beep input is powered-up. and when the beeps bit is set to ? 1 ? , the input signal from the beep pin is output to speaker-amp. when the beepa bit is set to ? 1 ? , the input signal from the beep pin is output to the mono line output amplifier. the external resister ri adjusts the signal level of beep input. the gains are shown in table 18, when ri = 20k ? . these gain are in inverse proportion to ri. beep - + rf ri figure 32. block diagram of beep pin spkg1-0 bits beep ? spp/spn gain beep ? aout gain 00 +7.89db 0db 01 +9.93db 0db 10 +14.11db 0db 11 +16.15db 0db table 18. beep input gain at r i = 20k ?
asahi kasei [ak4632] ms0396-e-00 2005/06 - 35 - ? mono line output (aout pin) a signal of dac is output from aout pin. when the daca bit is ? 0 ? , this output is off. the load resistance is 10k ? (min). when pmao bit is ? 0 ? and aopsn bit is ? 0 ? , the mono line output enters power-down and is pulled down by 100 ? (typ). if pmao bit is controlled at aopsn bit = ? 1 ? , pop noise will be reduced at power-up and down. then, this line should be pulled down by 20k ? of resister after c-coupling shown in figure 33. this rising and falling time is max 300 ms at c=1.0 f . when pmao bit is ? 1 ? and aopsn bit is ? 0 ? , the mono line output enters power-up state. aout 1 ? ? figure 33. aout external circuit in case of using pop reduction function. aout control sequence in case of using pop reduction circuit pmao bit a opsn bit a out pin (1) (2) norm al output (3) (4) (5) (6) 300 m s 300 m s figure 34. mono line output control sequence in case of using pop reduction function.. (1) set aopsn bit = ? 1 ? . mono line output enters the power-save mode. (2) set pmao bit = ? 1 ? . mono line output exits the power-down mode. aout pin rises up to vcom voltage. rise time is 200ms (max 300ms) at c=1 f. (3) set aopsn bit = ? 0 ? after aout pin rises up. mono line output exits the power-save mode. mono line output is enabled. (4) set aopsn bit = ? 1 ? . mono line output enters power-save mode. (5) set pmao bit = ? 1 ? . mono line output enters power-down mode. aout pin falls down to avss. fall time is 200ms (max 300ms) at c=1 f. (6) set aopsn bit = ? 0 ? after aout pin falls down. mono line output exits the power-save mode.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 36 - ? speaker output the power supply voltage for speaker-amp svdd can be set to from 2.6v to 5.25v. however, svdd should be set to from 2.6v to 3.6v, when the load resistance is less than 50 ? (ex. a dynamic speaker). the output signal from dac is input to the speaker-amp via the alc2 circuit. this speaker-amp is a mono output controlled by btl and a gain of the speaker-amp is set by spkg1-0 bit. in the case of alc2 off, the output voltage depends on avdd and spkg1-0 bits. in the case of alc2 on, the output voltage depends on svdd and spkg1-0 bits. the output level of alc2 is proportional to svdd. spkg1-0 bits gain 00 0db 01 +2.04db 10 +6.22db 11 +8.26db (note) these gain from the level at spkg1-0bits= ? 00 ? . table 19. gain of speaker-amp at alc2 off spkg1-0 bits avdd svdd output voltage from speaker-amp at alc2 off and dac input=0dbfs output voltage from speaker-amp at alc on 00 3.3v 3.3v 3.27vpp, 167mw@8 ? 3.09vpp, 150mw@8 ? 01 3.3v 3.3v 4.15vpp, 269mw@8 ? 3.92vpp, 240mw@8 ? 10 3.3v 3.3v 6.91vpp (note) not available 11 3.3v 3.3v 8.50vpp (note) not available 00 3.3v 5.0v 3.27vpp not available 01 3.3v 5.0v 4.15vpp not available 10 3.3v 5.0v 6.91vpp 6.34vpp 11 3.3v 5.0v 8.50vpp 8.02vpp (note) this output voltage is assumed that the signal is not clipped. in actual, the signal will be clipped when dac outputs 0dbfs signal. the output power is 400mw@8 ? , svdd=3.3v. table 20. speaker-amp output voltage [caution for using piezo speaker] when a piezo speaker (load capacitance > 30pf) is used, resistances more than 10 ? should be inserted between spp/spn pins and speaker in series, respectively, as shown in figure 35. zener diodes should be inserted between speaker and gnd as shown in figure 35, in order to protect spk-amp of ak4632 from the power that the piezo speaker outputs when the speaker is pressured. zener diodes of the following zener voltage should be used. 92% of svdd zener voltage of zener diodo(zd of figure 35) svdd+0.3v ex) in case of svdd = 5.0v : 4.6v zd 5.3v for example, zener diode which zener voltage is 5.1v(min :4.97v, max 5.24v) can be used.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 37 - spp spk-amp spn 10 ? 10 ? figure 35. circuit of speaker output(load capacitance > 30pf) speaker blocks (mout, alc2 and speaker-amp) can be powered-up/down by controlling the pmspk bit. when the pmspk bit is ? 0 ? , the mout, spp and spn pins are placed in a hi-z state. when the pmspk bit is ? 1 ? and spps bit is ? 0 ? , the speaker-amp enters power-save-m ode. in this mode, the spp pin is placed in a hi-z state and the spn pin goes to svdd/2 voltage. and then the speaker output gradually changes to the svdd/2 voltage and this mode can reduce pop noise at power -up. when the ak4632 is powered-down, pop noise can be also reduced by first entering power-save-mode. pmspk bit spps bit spp pin spn pin svdd/2 svdd/2 hi-z hi-z hi-z hi-z >t1(note) >0 figure 36. power-up/power-down timing for speaker-amp (note) ? t1 ? depends on the time constant of input resistance of min and capacitor between mout pin and min pin. if s peaker-amp output is enabled before min-amp (alc2) becomes stable, pop noise may occur. ex) c of mout pin ? min pin = 0.1 f, input resistance of min pin = 36k ? (max) : t1 = 5 = 18ms c of mout pin ? min pin and the input resistance(rin) of min pin compose of hpf which cut off frequency(fc) are the followings. fc = 66hz@rin=24k ? (typ), 133hz@rin=12k ? (min), 44hz@rin=36k ? (max)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 38 - ? spk-alc operation the alc (automatic level control) operation of speaker output is done by alc2 block when alc2 bit is ? 1 ? . input resistance of the alc2 is 24k ? (typ) and centered around vcom voltage. the alc2 level diagram is shown in figure 37 ~ figure 40. the limiter detection level is proportional to svdd voltage. the output level is limited by the alc2 circuit when the input signal exceeds ?7.1dbv (@spkg1 bit = ? 0 ? , svdd=3.3v or @spkg1 bit = ? 1 ? , svdd = 5v). when a continuous signal of ?7.1dbv or greater is input to the alc2 circuit, the change period of the alc2 limiter operation is 250 s (=2/fs@fs=8khz) and the attenuation level is 0.5db/step. the alc2 recovery operation uses zero crossings and gains of 1db/step. the alc2 recovery operation is done until the input level of the speaker-amp goes to ?9.1dbv (@spkg1 bit = ? 0 ? , svdd=3.3v or @spkg1 bit = ? 1 ? , svdd = 5v). maximum gain of the alc2 recovery operation is set by rfs5-0 bits. when the input signal is between ?9.1dbv and ?7.1dbv, the alc2 limiter or recovery operations are not done. when the pmspk bit changes from ? 0 ? to ? 1 ? , the initilization cycle (512/fs = 64ms @fs=8khz at rotm bit = ? 0 ? ) starts. the alc2 is disabled (the alc2 gain is fixed to ? -3.5db ? .) during the initilization cycle and the alc2 starts from ? ?2db ? after completing the initilization cycle. the rotm bit and rfs5-0 bits set during the pmspk bit = ? 0 ? . when the alc2 is disable, a gain of the alc2 block is fixed to -3.5db. therefore, a gain of internal speaker block is shown in table 22. parameter alc2 limiter operation alc2 recovery operation operation start level ? 5.2dbv ? 7.2dbv fs=8khz 2/fs = 250 s 512/fs=64ms period fs=16khz 2/fs = 125 s 512/fs=32ms zero-crossing detection no yes (timeout = period time) att/gain 0.5db step 1db step table 21. limiter /recovery of alc2 (rotm bit = ? 0 ? ) spkg1-0 bits gain 00 +4.4db 01 +6.4db 10 +10.6db 11 +12.7db table 22. gain of speaker-amp at alc2 off(full-differential output)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 39 - -15.1dbv fs fs-12db 0dbv fs-4.0db = -7.1dbv -1.2dbv full-differential -3.1dbv -10dbv -5.2dbv -20dbv -30dbv -23.1dbv -8db -15.1dbv -11.1dbv -3.1dbv fs-6.0db = -9.1dbv +6.0db +14.0db +2.0db -4.0db +7.9db -8db single-ended dvol dac alc2 spk-amp 0.8dbv +7.9db +1.9db (avdd=3.3v, svdd=3.3v, dvol= ? 8.0db/0db, spkg1-0 bit = ? 00 ? ,) * fs = full scale figure 37. speaker-amp output level diagram -15.1dbv fs fs-12db 0dbv fs-4db = -7.1dbv 0.8dbv full-differential -3.1dbv -10dbv -3.2dbv -20dbv -30dbv -23.1dbv -8db -15.1dbv -11.1dbv -3.1dbv fs-6.0db = -9.1dbv +6.0db +14.0db +2.0db -4.0db +9.9db -8db single-ended dvol dac alc2 spk-amp 2.8dbv +9.9db +3.9db 10dbv (avdd=3.3v, svdd=3.3v, dvol= ? 8.0db/0db, spkg1-0 bit = ? 01 ? ,) * fs = full scale figure 38. speaker-amp output level diagram
asahi kasei [ak4632] ms0396-e-00 2005/06 - 40 - -15.1dbv fs fs-12db 0dbv fs-4db = -7.1dbv 5.0dbv full-differential -3.1dbv -10dbv 1.0dbv -20dbv -30dbv -23.1dbv -8db -15.1dbv -11.1dbv -3.1dbv fs-6.0db = -9.1dbv +6.0db +14.0db +2.0db -4.0db +14.1db -8db single-ended dvol dac alc2 spk-amp 7.0dbv +14.1db +8.1db 10dbv (avdd=3.3v, svdd=5.0v, dvol= ? 8.0db/0db, spkg1-0 bit = ? 10 ? ,) * fs = full scale figure 39. speaker-amp output level diagram -15.1dbv fs fs-12db 0dbv fs-4db = -7.1dbv 7.1dbv full-differential -3.1dbv -10dbv 3.1dbv -20dbv -30dbv -23.1dbv -8db -15.1dbv -11.1dbv -3.1dbv fs-6.0db = -9.1dbv +6.0db +14.0db +2.0db -4.0db +16.2db -8db single-ended dvol dac alc2 spk-amp 9.1dbv +16.2db +10.2db 10dbv (avdd=3.3v, svdd=5.0v, dvol= ? 8.0db/0db, spkg1-0 bit = ? 11 ? ,) * fs = full scale figure 40. speaker-amp output level diagram
asahi kasei [ak4632] ms0396-e-00 2005/06 - 41 - ? video block video-amp has a drivability for a load resistance of 150 ? . the ak4632 has a composite input and output. a low pass filter(lpf) and gain control amp(gca) are integrat ed and both dc output and sag compensation circuit are supported as shown in figure 41 and figure 42. the capacitance for sag compensation circuit is 100 f+2.2 f or 47 f+1.0 f. when dc output is used, vout pin and vsag pin must be shorted. the output clamp voltage is 150mv(typ) at dc output. sagc1-0 bits and vvdd voltage should be set as shown in table 23. table 25 shows the gain and step of the gain control. the gain is set by vgca4-0 bits. pmv bit c ontrols the power up and down of the video block. vout pin outputs avss level at pmv bit = ? 1 ? . yin vout clamp 75 ? vsag lpf gca c1 c2 +6db -1db ~ +10.5db step 0.5db (c1=100 f, c2=2.2 f) or (c1=47 f, c2=1.0 f) figure 41. video block (using sag compensation circuit) yin vout clamp 75 ? vsag lpf gca +6db -1db ~ +10.5db step 0.5db figure 42. video block (at dc output)) sagc1 bit sagc0 bit vvdd voltage output circuit 0 0 2.8 v vvdd 3.6v dc output default 0 1 not available 1 0 2.85v vvdd < 4.75v sag compensation 1 1 4.5 v vvdd < 5.25v sag compensation table 23. setting of vvdd and video output circuit. output circuit vvdd voltage gca setting dc output 2.8 v vvdd 3.6v 0db sag compensation 100 f+2.2 f 3.135 v vvdd 5.25v 0db 2.85v vvdd < 3.135 v -1db (note) sag compensation 47 f+1.0 f 3.135 v vvdd 5.25v 0db 2.85v vvdd < 3.135 v -1db (note) note : when the sag compensation circuit is used at less than 3.135v of vvdd, the gca should be set to -1db in order to avoid clipping of output video signal. note that the video will become dark at that time. table 24. gain compensation
asahi kasei [ak4632] ms0396-e-00 2005/06 - 42 - vgca4-0 bits gain(db) step 17h +10.5db 16h +10.0db 15h +9.5db : : 0.5db 04h +1.0db 03h +0.5db 02h 0.0db default 01h -0.5db 00h -1.0db table 25. setting of gca ? serial control interface internal registers may be written by using the 3-wire p interface pins (csn, cclk and cdti). the data on this interface consists of a 2-bit chip address (fixed to ? 10 ? ), read/write (fixed to ? 1 ? ), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized at pdn pin = ? l ? . csn cclk 0 1 2 345 67891011 12 13 14 15 cdti c1 c0 a 2 a 3 a 2 a 0 a 4 d7d6d5d4d3d2d1d0 r/w c1-c0: chip address (c1 = ?1?, c0 = ?0?); fixed to ?10? r/w: read/write (?1?: write, ?0?: read); fixed to ?1? a 4-a0: register address d7-d0: control data ?1? ?0? ?1? figure 43. serial control i/f timing
asahi kasei [ak4632] ms0396-e-00 2005/06 - 43 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmbp pmspk pmao pmdac pmmic pmadc 01h power management 2 pmv 0 0 0 m/s mckpd mcko pmpll 02h signal select 1 spps beeps alc2s daca dacm mpwr micad mgain0 03h signal select 2 0 aopsn mgai n1 spkg1 spkg0 beepa alc1m alc1a 04h mode control 1 pll3 pll2 pll1 pll0 bcko1 bcko0 dif1 dif0 05h mode control 2 0 0 fs3 msbs bckp fs2 fs1 fs0 06h timer select dvtm rotm ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 07h alc mode control 1 0 alc2 al c1 zelm lmat1 lmat0 ratt lmth 08h alc mode control 2 0 ref6 re f5 ref4 ref3 ref2 ref1 ref0 09h input pga control 0 ipga6 ipga 5 ipga4 ipga3 ip ga2 ipga1 ipga0 0ah digital volume control dvol7 dv ol6 dvol5 dvol4 dvol3 dvol2 dvol1 dvol0 0bh alc2 mode control 0 0 rfs5 rfs4 rfs3 rfs2 rfs1 rfs0 0ch video mode control 0 sagc1 sagc0 vgca4 vgca3 vgca2 vgca1 vgca0 the pdn pin = ? l ? resets the registers to their default values. note: unused bits must contain a ? 0 ? value. note: only write to address 00h to 0ch.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 44 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmbp pmspk pmao pmdac pmmic pmadc default 0 0 0 0 0 0 0 0 pmadc: adc block power control 0: power down (default) 1: power up when the pmadc bit changes from ? 0 ? to ? 1 ? , the initialization cycle (1059/fs=133ms@8khz) starts. after initializing, digital data of the adc is output. pmmic: mic in block (mic-amp and alc1) power control 0: power down (default) 1: power up pmdac: dac block power control 0: power down (default) 1: power up pmao: mono line out power control 0: power down (default) 1: power up pmspk: speaker block power control 0: power down (default) 1: power up pmbp: beep in power control 0: power down (default) 1: power up even if pmbp bit is ? 0 ? , the path is still connected between beep and aout/spk-amp. beeps and beepa bits should be set to ? 0 ? to disconnect these paths. pmvcm: vcom block power control 0: power down (default) 1: power up each block can be powered-down respectively by writing ? 0 ? in each bit. when the pdn pin is ? l ? , all blocks are powered-down. when pmpll and mcko bits and all bits in 00h address are ? 0 ? , all blocks are powered-down. though the ipga resisters are initialized, the other registers remain unchanged. (refer to the ipga6-0 bits description) when any of the blocks are powered-up, the pmvcm bit must be set to ? 1 ? . when pmpll and mcko bits and all bits in 00h address are ? 0 ? , pmvcm bit can write to ? 0 ? . when beep signal is output from speaker-amp (signal path: beep pin ? spp/spn pins) or mono lineout-amp (signal path: beep pin ? aout pin) only, the clocks may not be present. when adc, dac, alc1 or alc2 is in operation, the clocks must always be present.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 pmv 0 0 0 m/s mckpd mcko pmpll default 0 0 0 0 0 1 0 0 pmpll: pll block power control select 0: pll is power down and external is selected. (default) 1: pll is power up and pll mode is selected. mcko: master clock output enable 0: ? l ? output (default) 1: 256fs output mckpd: mcki pin pull down control 0: master clock input enable 1: pull down by 25k ? (typ.) (default) m/s: select master / slave mode 0: slave mode (default) 1: master mode pmv: video block power control 0: power down (default) 1: power up
asahi kasei [ak4632] ms0396-e-00 2005/06 - 46 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 spps beeps alc2s daca dacm mpwr micad mgain0 default 0 0 0 0 0 0 0 1 mgain1-0 : 1 st mic-amp gain control(see table 26) mgain 1 bit is located at d6 bit of 03h mgain1 bit mgain0 bit input gain 0 0 0db 0 1 +20db default 1 0 +26db 1 1 +32db table 26. input gain micad: switch control from mic in to adc. 0: off (default) 1: on when micad bit is ? 1 ? , the alc1 output signal is input to adc. mpwr: power supply control for microphone 0: off (default) 1: on when pmmic bit is ? 1 ? , mpwr bit is enabled. dacm: switch control from dac to mono amp. 0: off (default) 1: on when pmspk bit is ? 1 ? , dacm bit is enabled. when pmspk bit is ? 0 ? , mout pin is hi-z state. daca: switch control from dac to mono line amp 0: off (default) 1: on when pmao bit is ? 1 ? , daca bit is enabled. when pmao bit is ? 0 ? , the aout pin is avss. alc2s: alc2 output to speaker-amp enable 0: off (default) 1: on when alc2s bit is ? 1 ? , the alc2 output signal is input to speaker-amp. beeps: beep pin to speaker-amp enable 0: off (default) 1: on when beeps bit is ? 1 ? , the beep signal is input to speaker-amp. spps: speaker-amp power-save-mode 0: power save mode (default) 1: normal operation when spps bit is ? 1 ? , the speaker-amp is in power-save-mode and the spp pin becomes hi-z and spn pin is set to svdd/2 voltage. when the pmspk bit = ? 1 ? , this bit is valid. after the pdn pin changes from ? l ? to ? h ? , the pmspk bit is ? 0 ? , which powers down speaker-amp.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 47 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 0 0 mgain1 spkg1 spkg0 beepa alc1m alc1a default 0 0 0 0 0 0 0 0 alc1a: switch control from alc1 output signal to mono line output amp. 0: off (default) 1: on when pmao bit is ? 1 ? , alc1a bit is enabled. when pmao bit is ? 0 ? , the aout pin is avss. alc1m: switch control from alc1 output signal to mono amp. 0: off (default) 1: on when pmspk bit is ? 1 ? , alc1m is enabled. when pmspk bit is ? 0 ? , the mout pin goes hi-z state. beepa: switch control from beep signal to mono line output amp. 0: off (default) 1: on when pmao bit is ? 1 ? , beepa is enabled. when pmao bit is ? 0 ? , the aout pin is avss. spkg1-0: select speaker-amp output gain (see table 27) spkg1-0 bits gain 00 0db 01 +2.2db 10 +4.4db 11 +8.7db table 27. gain of speaker-amp mgain1: mic-amplifier gain control(see table 26) dac mix alc2 alc2s spk ipga dacm alc1m aout beep beeps alc1a daca beepa figure 44. speaker and mono lineout-amps switch control
asahi kasei [ak4632] ms0396-e-00 2005/06 - 48 - aopsn: mono line output power-save mode 0: normal operation 1: power-save mode (default) power-save mode is enable at aopsn bit = ? 1 ? . pop noise at power-up/down can be reduced by changing at aopsn bit = ? 1 ? . (see figure 34) addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 pll3 pll2 pll1 pll0 bcko1 bcko0 dif1 dif0 default 0 0 0 0 0 0 1 0 dif1-0: audio interface format (see table 28) mode dif1 bit dif0 bit sdto (adc) sdti (dac) bick figure 0 0 0 dsp mode dsp mode 16fs see table 34 1 0 1 msb justified lsb justified 32fs figure 27 2 1 0 msb justified msb justified 32fs figure 28 default 3 1 1 i 2 s compatible i 2 s compatible 32fs figure 29 table 28. audio interface format bcko1-0: select bick output frequency at master mode (see table 29) mode bcko1 bit bcko0 bit bick output frequency 0 0 0 16fs default 1 0 1 32fs 2 1 0 64fs 3 1 1 n/a table 29. bick output frequency at master mode pll3-0: select input frequency at pll mode (see table 30) mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency 0 0 0 0 0 fck pin 1fs default 1 0 0 0 1 bick pin 16fs 2 0 0 1 0 bick pin 32fs 3 0 0 1 1 bick pin 64fs 4 0 1 0 0 mcki pin 11.2896mhz 5 0 1 0 1 mcki pin 12.288mhz 6 0 1 1 0 mcki pin 12mhz 7 0 1 1 1 mcki pin 24mhz 12 1 1 0 0 mcki pin 13.5mhz 13 1 1 0 1 mcki pin 27mhz others others n/a table 30. setting of pll mode (*fs: sampling frequency)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 49 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 0 0 fs3 msbs bckp fs2 fs1 fs0 default 0 0 0 0 0 0 0 0 fs3-0: setting of sampling frequency (see table 31 and table 32) and mcki frequency (see table 33) these bits are selected to sampling frequency at pll mode and mcki frequency at ext mode. mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz default 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 5 0 1 0 1 11.025khz 6 0 1 1 0 14.7khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 15 1 1 1 1 44.1khz others others n/a table 31. setting of sampling frequency at pll2 bit = ? 1 ? and pmpll bit = ? 1 ? mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 don?t care 0 0 7.35khz fs 8khz default 1 0 don?t care 0 1 8khz < fs 12khz 2 0 don?t care 1 0 12khz < fs 16khz 3 0 don?t care 1 1 16khz < fs 24khz 6 1 don?t care 1 0 24khz < fs 32khz 7 1 don?t care 1 1 32khz < fs 48khz others others n/a table 32. setting of sampling frequency at pll2 bit = ? 0 ? and pmpll bit = ? 1 ? mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz fs 48khz default 1 don?t care 0 1 1024fs 7.35khz < fs 13khz 2 don?t care 1 0 256fs 7.35khz < fs 48khz 3 don?t care 1 1 512fs 7.35khz < fs 26khz table 33. mcki frequency at ext slave mode (pmpll bit = ? 0 ? , m/s bit = ? 0 ? ) bckp, msbs: ? 00 ? (default) (see table 34) msbs bit bckp bit audio interface format 0 0 figure 23 default 0 1 figure 24 1 0 figure 25 1 1 figure 26 table 34. audio interface format in mode 0
asahi kasei [ak4632] ms0396-e-00 2005/06 - 50 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h timer select dvtm rotm ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 default 0 0 0 0 0 0 0 0 ltm1-0: alc1 limiter opera tion period at zero cros sing disable (zelm bit = ? 1 ? ) (see table 35) the ipga value is changed immediately. when the ipga value is changed continuously, the change is done by the period specified by the ltm1-0 bits. default is ? 00 ? (0.5/fs). alc1 limiter operation period ltm1 bit ltm0 bit 8khz 16khz 0 0 0.5/fs 63 s 31 s default 0 1 1/fs 125 s 63 s 1 0 2/fs 250 s 125 s 1 1 4/fs 500 s 250 s table 35. alc1 limiter op eration peri od at zero crossing disable (zelm bit= ? 1 ? ) wtm1-0: alc1 recovery waiting period (see table 36) a period of recovery operation when any limiter operation does not occur during the alc1 operation. default is ? 00 ? (128/fs). alc1 recovery operation waiting period wtm1 bit wtm0 bit 8khz 16khz 0 0 128/fs 16ms 8ms default 0 1 256/fs 32ms 16ms 1 0 512/fs 64ms 32ms 1 1 1024/fs 128ms 64ms table 36. alc1 recovery operation waiting period ztm1-0: alc1 zero crossing timeout period (see table 37) when the ipga perform zero crossing or timeout, the ipga value is changed by the p write operation, alc1 recovery operati on or alc1 limiter operation (zelm bit = ? 0 ? ). default is ? 00 ? (128/fs). zero crossing timeout period ztm1 bit ztm0 bit 8khz 16khz 0 0 128/fs 16ms 8ms default 0 1 256/fs 32ms 16ms 1 0 512/fs 64ms 32ms 1 1 1024/fs 128ms 64ms table 37. zero crossing timeout period rotm: period time for alc2 recovery operation, alc2 zero crossing timeout and alc2 initializing cycle. 0: 512/fs (default) 1: 1024/fs the rotm bit is set during the pmspk bit = ? 0 ? . dvtm : digital volume soft transition time control 0: 1061/fs (default) 1: 256/fs this is the time to ffh from 00h of dvol7-0 bits.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 51 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h alc mode control 1 0 alc2 alc1 zelm lmat1 lmat0 ratt lmth default 0 1 0 0 0 0 0 0 lmth: alc1 limiter detection level / recovery waiting counter reset level (see table 38 ) the alc1 limiter detection level and the alc1 recovery counter reset level may be offset by about 2db. default is ? 0 ? . lmth bit alc1 limiter detection level alc1 recovery waiting counter reset level 0 adc input ? 6.0dbfs ? 6.0dbfs > adc input ? 8.0dbfs default 1 adc input ? 4.0dbfs ? 4.0dbfs > adc input ? 6.0dbfs table 38. alc1 limiter detection level / recovery waiting counter reset level ratt: alc1 recovery gain step (see table 39) during the alc1 recovery operation, the number of steps changed from the current ipga value is set. for example, when the current ipga value is 30h and ratt bit = ? 1 ? is set, the ipga changes to 32h by the alc1 recovery operation and the output signal level is gained up by 1db (=0.5db x 2). when the ipga value exceeds the reference level (ref6-0 bits), the ipga value does not increase. ratt bit gain step 0 1 default 1 2 table 39. alc1 recovery gain step setting lmat1-0: alc1 limiter a tt step (see table 40) during the alc1 limiter operation, when ipga output signal exceeds the alc1 limiter detection level set by lmth, the number of steps attenuated from the current ipga value is set. for example, when the current ipga value is 47h and the lmat1-0 bits = ? 11 ? , the ipga transition to 43h when the alc1 limiter operation starts, resulting in the input signal level being attenuated by 2db (=0.5db x 4). when the attenuation value exceeds ipga = ? 00 ? ( ? 8db), it clips to ? 00 ? . lmat1 bit lmat0 bit att step 0 0 1 default 0 1 2 1 0 3 1 1 4 table 40. alc1 limite r att step setting zelm: enable zero cro ssing detection at al c1 limiter operation 0: enable (default) 1: disable when the zelm bit = ? 0 ? , the ipga of each l/r channel perform a zero crossing or timeout independently and the ipga value is changed by the alc1 operation. the zero crossing timeout is the same as the alc1 recovery opera tion. when the zelm bit = ? 1 ? , the ipga value is changed immediately.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 52 - alc1: alc1 enable 0: alc1 disable (default) 1: alc1 enable when alc1 bit is ? 1 ? , the alc1 operation is enabled. alc2: alc2 enable 0: alc2 disable 1: alc2 enable (default) after completing the initializing cycle (512/fs = 64ms @fs=8khz at rotm bit = ? 0 ? ), the alc2 operation is enabled. when the pmspk bit changes from ? 0 ? to ? 1 ? or pdn pin changes from ? l ? to ? h ? , the initilization cycle starts. addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h alc mode control 2 0 ref6 re f5 ref4 ref3 ref2 ref1 ref0 default 0 0 1 1 0 1 1 0 ref6-0: reference value at alc1 recovery operation (see table 41) during the alc1 recovery operation, if the ipga value exceeds the setting reference value by gain operation, then the ipga does not become larger than the reference value. for example, when ref7-0 = ? 30h ? , ratt = 2step, ipga = 2fh, even if the input signal does not exceed the ? alc1 recovery waiting counter reset level ? , the ipga does not change to 2fh + 2step = 31h, and keeps 30h. default is ? 36h ? . data (hex) gain (db) step 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 default : : 10 +0.0 : : 06 ? 5.0 05 ? 5.5 04 ? 6.0 03 ? 6.5 02 ? 7.0 01 ? 7.5 00 ? 8.0 0.5db table 41. setting reference value at alc1 recovery operation
asahi kasei [ak4632] ms0396-e-00 2005/06 - 53 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h input pga control 0 ipga6 ip ga5 ipga4 ipga3 ipga2 ipga1 ipga0 default 0 0 0 1 0 0 0 0 ipga6-0: input analog pga (see table 42) default: ? 10h ? (0db) when ipga gain is changed, ipga6-0 bits should be written while pmmic bit is ? 1 ? and alc1 bit is ? 0 ? . ipga6-0 bits should be set at 2/fs(250 s@fs=8khz) after pmmic bit is set to ? 1 ? . ipga gain is reset when pmmic bit is ? 0 ? , and then ipga operation starts from the default value when pmmic bit is changed to ? 1 ? . when alc1 bit is changed from ? 1 ? to ? 0 ? , ipga holds the last gain value set automatically by alc1 operation. in a manual mode, ipga can be set to any values in table 42.the ztm1-0 bits set zero crossing timeout period when ipga value is changed. when the control register is written from the p, the zero crossing counter is reset and its counter starts. when the signal zero crossing or zero crossing timeout, the written value from the p becomes valid. data (hex) gain (db) step 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 : : 10 +0.0 default : : 06 ? 5.0 05 ? 5.5 04 ? 6.0 03 ? 6.5 02 ? 7.0 01 ? 7.5 00 ? 8.0 0.5db table 42. input gain setting addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah digital volume control dvol7 dvol6 dvol5 dvol4 dvol3 dvol2 dvol1 dvol0 default 0 0 0 1 1 0 0 0 dvol7-0: output digital volume (see table 43) the ak4632 has a digital output volume (256 levels, 0.5db step, mute). the gain can be set by the dvol7-0 bits. the volume is included in front of a dac block, a input data of dac is changed from +12 to ?115db with mute. this volume has a soft transition function. it takes 1061/fs (=133ms @ fs = 8khz) or 256/fs (=32ms @ fs = 8khz) from 00h to ffh. soft transition time is set by dvtm bit. dvol7-0 gain 00h +12.0db 01h +11.5db 02h +11.0db ? ? 18h 0db default ? ? fdh ? 114.5db feh ? 115.0db ffh mute ( ? ) table 43. digital volume code table
asahi kasei [ak4632] ms0396-e-00 2005/06 - 54 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh alc2 mode control 0 0 r fs5 rfs4 rfs3 rfs2 rfs1 rfs0 default 0 0 1 1 1 1 0 0 rfs6-0: reference value at alc2 recovery operation (see table 44) refs5-0 bits volume[db] step 3f +19.5 3e +19.0 3d +18.5 3c +18.0 default : : 0.5db 19 +0.5 18 +0.0 17 -0.5 : : 03 -10.5 02 -11.0 01 -11.5 00 -12.0 table 44. setting reference value at alc2 recovery operation addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch video mode control 0 sagc1 sagc0 vgca4 vgca3 vgca2 vgca1 vgca0 default 0 0 0 0 0 0 1 0 vgca4-0: gain control of video output(see table 25) sagc1-0: select video output circuit (see table 23)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 55 - system design figure 45 shows the system connection diagram. an evaluation board [akd4632] is available which demonstrates the optimum layout, power supply arrangements and measurement results. 25 mout csn 9 top vie w a nalog supply 2.6 3.6v dsp or p + 0.1 10 + 0.1 0.1 1 10 0.1 a nalog suppl y 2.6 5.25v 0.1 10 + cp rp 2.2k 0.22 r c 1 10 + speaker 20k 220 r1 r2 zd2 zd1 dynamic spk : r1,r2 : short zd1,zd2 : open peizo spk : r1,r2 : 10 ? zd1,zd2 : required vcom 32 a vdd 2 a vss 3 vvdd 4 vin 5 vout 6 vsag 7 pdn 8 cclk 10 sdti 12 cdti 11 fck 14 sdto 13 vcoc 1 bick 15 dvdd 26 aout 27 beep 28 ain 29 micout 30 mic 31 mpi 16 75 0.1u cv cs 10 0.1 10 24 23 22 21 20 19 18 17 min svss svdd spp spn mcko mcki dvss a nalog supply 2.8 5.25v sagc1-0 bits = ?00? cv : short cs : short sagc1-0 bits = ?10? or ?11? cv=100 f & cs=2.2 f or cv=47 f & cs=1.0 f figure 45. typical connection diagram notes: - avss, dvss and svss of the ak4632 should be distributed separately from the ground of external controllers. - the exposed pad on the bottom surface of the package must be open. - all digital input pins except pull-down pin should not be left floating. - value of r and c of beep pin should depend on system. - when the ak4632 is ext mode (pmpll bit = ? 0 ? ), a resistor and capacitor of vcoc pin is not needed. - when the ak4632 is pll mode (pmpll bit = ? 1 ? ), a resistor and capacitor of vcoc pin is shown in table 45. - input resistance of ain pin and capacitance between micout pin and ain pin compose of hpf. when the capacitance is 0.22 f, the cut off frequency is typ. 72hz(typ)(min. 48hz, max. 145hz). rp and cp of vcoc pin mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency rp[ ? ] cp[f] pll lock time (max) 0 0 0 0 0 fck pin 1fs 6.8k 220n 160ms default 1 0 0 0 1 bick pin 16fs 10k 4.7n 2ms 2 0 0 1 0 bick pin 32fs 10k 4.7n 2ms 3 0 0 1 1 bick pin 64fs 10k 4.7n 2ms 4 0 1 0 0 mcki pin 11.2896mhz 10k 4.7n 40ms 5 0 1 0 1 mcki pin 12.288mhz 10k 4.7n 40ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 40ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 40ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 40ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 40ms others others n/a table 45. setting of pll mode (*fs: sampling frequency)
asahi kasei [ak4632] ms0396-e-00 2005/06 - 56 - 1. grounding and power supply decoupling the ak4632 requires careful attention to power supply and grounding arrangements. avdd, dvdd, svdd and vvdd are usually supplied from the system?s analog supply. if avdd, dvdd, svdd and vvdd are supplied separately, the correct power up sequence should be obs erved. avss, dvss and svss of the ak4632 should be connected to the analog ground plane. system analog ground and digital ground s hould be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4632 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak4632. 3. analog inputs the mic and beep inputs are single-ended. the input signal range scales with nominally at 0.06 x avdd vpp for the mic input and 0.6 x avdd vpp for the beep input, centered around the internal common voltage (approx. 0.45 x avdd). usually the input signal is ac coupled using a capacitor. the cut-off frequency is fc = (1/2 rc). the ak4632 can accept input voltages from avss to avdd. 4. analog outputs the input data format for the dac is 2?s complement. the output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). mono output from the mout pin and mono line output from the aout pin are centered at 0.45 x avdd (typ). the speaker-amp output is centered at svdd/2.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 57 - control sequence ? clock set up when adc, dac, alc1, alc2 and ipga are used, the clocks must be supplied. 1. in case of pll master mode. mckpd bit (addr:01h, d2) bick pin fck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) 40msec(max) output (1) (4) (7) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (6) (5) input m/s bit (addr:01h, d3) 1msec (max) (8) mcko pin output (10) (9) 40msec(max) example: audio i/f format: dsp mode, bckp = msbs = ?0? bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko : enable sampling frequency:8khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:40h (2)addr:01h, data:0ch addr:04h, data:48h addr:05h, data:00h (4)addr:01h, data:0bh mcko, bick and fck output figure 46. clock set up sequence (1) (1) after power up, pdn pin = ? l ? ? h ? ? l ? time (1) of 150ns or more is needed to reset the ak4632. (2) dif1-0, pll3-0, fs3-0, bcko1-0, msbs, bckp and m/s bits should be set during this period. (3) power upvcom: pmvcm bit = ? 0 ? ? 1 ? vcom should first be powered-up before the other block operates. (4) release the pull-down resistor of the mcki pin: mckpd bit = ? 1 ? ? 0 ? (5) in case of using mcko output: mcko bit = ? 1 ? in case of not using mcko output: mcko bit = ? 0 ? (6) pll lock time is 40ms(max) after pmpll bit changes from ? 0 ? to ? 1 ? and mcki is supplied from an external source. (7) the ak4632 starts to output the fck and bick clocks after the pll becomes stable. the normal operation of the block which a clock is necessary for becomes possible. (8) the invalid frequencies are output from fck and bick pins during this period. (9) the invalid frequency is output from mcko pin during this period. (10) the normal clock is output from mcko pin after the pll is locked.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 58 - 2. when the external clocks (fck or bick pin) are used in pll slave mode. mckpd bit (addr:01h, d2) pmpll bit (addr:01h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) fck pin bick pin (5) "h" (6) input (4) 4fs of example: audio i/f format : dsp mode, bckp = msbs = ?0? pll reference clock: bick bick frequency: 64fs sampling frequency: 8khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:30h addr:05h, data:00h (4) addr:01h, data:05h bick and fck input figure 47. clock set up sequence (2) (1) after power up: pdn pin ? l ? ? h ? ? l ? time (1) of 150ns or more is needed to reset the ak4632. (2) dif1-0, fs3-0, pll3-0, msbs and bckp bits should be set during this period. (3) power up vcom: pmvcm bit = ? 0 ? ? 1 ? vcom should first be powered up before the other block operates. (4) pull down of the mcki pin: mckpd bit = ? 1 ? (5) pll starts after the pmpll bit changes from ? 0 ? to ? 1 ? and pll reference clock (fck or bick pin) is supplied. pll lock time is 160ms(max) when fck is a pll reference clock. and pll lock time is 2ms(max) when bick is a pll reference clock. (6) normal operation stats after the pll is locked.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 59 - 3. when the external clock (mcki pin) is used in pll slave mode. mckpd bit (addr:01h, d2) bick pin fck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) (1) (4) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (6) (5) input mcko pin output (7) (8) 40msec(max) (9) input example: audio i/f format: dsp mode, bckp = msbs = ?0? bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko : enable sampling frequency:8khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:40h (2)addr:01h, data:04h addr:04h, data:48h addr:05h, data:00h (4)addr:01h, data:03h mcko output start bick and fck input start figure 48. clock set up sequence (3) (1) after power up: pdn pin ? l ? ? h ? ? l ? time (1) of 150ns or more is needed to reset the ak4632. (2) dif1-0, pll3-0, fs3-0, bcko1-0, msbs, bckp and m/s bits should be set during this period. (3) power up vcom: pmvcm bit = ? 0 ? ? 1 ? vcom should first be powered up before the other block operates. (4) release the pull-down resistor of the mcki pin: mckpd bit = ? 1 ? ? 0 ? (5) enable mcko output: mcko bit = ? 1 ? (6) pll starts after the pmpll bit changes from ? 0 ? to ? 1 ? and pll reference clock (mcki pin) is supplied. pll lock time is 40ms(max). (7) the normal clock is output from mcko after pll is locked. (8) the invalid frequency is output from mcko during this period. (9) bick and fck clocks should be synchronized with mcko clock.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 60 - 4. ext slave mode mckpd bit (addr:01h, d2) (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) fck pin bick pin (5) input pmpll bit (addr:01h, d0) "l" (5) mcki pin input (4) example audio i/f format:msb justified (adc and dac) input mcki frequency: 1024fs sampling frequency:8khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:02h addr:05h, data:01h (4) addr:01h, data:00h mcki, bick and fck input figure 49. clock set up sequence (4) (1) after power up: pdn pin ? l ? ? h ? ? l ? time (1) of 150ns or more is needed to reset the ak4632. (2) dif1-0 and fs1-0 bits should be set during this period. (3) power up vcom: pmvcm bit = ? 0 ? ? 1 ? vcom should first be powered up before the other block operates. (4) release the pull-down resistor of the mcki pin: mckpd bit = ? 1 ? ? 0 ? power down pll: pmpll bit = ? 0 ? (5) normal operation starts after the mcki, fck and bick are supplied.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 61 - ? mic input recording fs3-0 bits (addr:05h, d5,d2-0) mic control (addr:02h, d2-0) pmadc bit (addr:00h, d0) pmmic bit (addr:00h, d1) adc internal state xxx xxxx 001 x1x power down initialize normal state power down 1059 / fs (1) (2) (6) (7) alc1 state alc1 enable alc1 disable alc1 disable (5) alc1 control 1 (addr:06h) xxh 00h (3) alc1 control 2 (addr:08h) xxh 47h (4) alc1 control 3 (addr:07h) xxh 61h or 21h example: pll master mode audio i/f format:dsp mode, bckp=msbs=?0? sampling frequency:8khz pre mic amp:+20db mic power on alc1 setting:refer to figrure 29 a lc2 bit=?1?(default) (2) addr:02h, data:07h (3) addr:06h, data:00h (1) addr:05h, data:00h (4) addr:08h, data:47h (5) addr:07h, data:61h (6) addr:00h, data:43h recording (7) addr:00h, data:40h figure 50. mic input recording sequence this sequence is an example of alc1 setting at s=8khz. if the parameter of the alc1 is changed, please refer to ? figure 31. registers set-up sequence at the alc1 operation ? at first, clocks should be supplied according to ? clock set up ? sequence. (1) set up a sampling frequency (fs3-0 bit). when the ak4632 is pll mode, mic and adc should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up mic input (addr: 02h) (3) set up timer select for alc1 (addr: 06h) (4) set up ref value for alc1 (addr: 08h) (5) set up lmth, ratt, lmat1-0 and alc1 bits (addr: 07h) (6) power up mic and adc: pmmic bit = pmadc bit = ? 0 ? ? 1 ? the initialization cycle time of adc is 1059/fs=133ms@fs=8khz. after the alc1 bit is set to ? 1 ? and mic block is powered-up, the alc1 operation starts from ipga default value (0db). (7) power down mic and adc: pmmic bit = pmadc bit = ? 1 ? ? 0 ? when the registers for the alc1 operation are not changed, alc1 bit may be keeping ? 1 ? . the alc1 operation is disabled because the mic block is powered-down. if the registers for the alc1 operation are also changed when the sampling frequency is changed, it should be done after the ak4632 goes to the manual mode (alc1 bit = ? 0 ? ) or mic block is powered-down (pmmic bit = ? 0 ? ). ipga gain is reset when pmmic bit is ? 0 ? , and then ipga operation starts from the default value when pmmic bit is changed to ? 1 ? .
asahi kasei [ak4632] ms0396-e-00 2005/06 - 62 - ? speaker-amp output fs2-0 bits (addr:05h, d5, d2-0) dvol7-0 bits (addr:0ah, d7-0) pmdac bit (addr:00h, d2) pmspk bit (addr:00h, d4) xxxx xxxx 0001100 xxxxxxx spp pin normal output spps bit (addr:02h, d7) hi-z hi-z spn pin normal output hi-z hi-z svdd/2 svdd/2 (1) (4) x 0 (3) alc2 bit (addr:07h, d6) (5) (6) (9) (7) (2) dacm bit (addr:02h, d3) alc2s bit (addr:02h, d5) (8) example: pll, master mode audio i/f format :dsp mode, bckp=msbs= ?0? sampling frequency: 8khz digital volume: -8db alc2 : enable (2) addr:02h, data:28h (3) addr:07h, data:40h (1) addr:05h, data:00h (4) addr:0ah, data:28h (5) addr:00h, data:54h (6) addr:02h, data:a8h (7) addr:02h, data:28h playback (8) addr:00h, data:40h figure 51. speaker-amp output sequence at first, clocks should be supplied according to ? clock set up ? sequence. (1) set up a sampling frequency (fs3-0 bits). when the ak4632 is pll mode, dac and speaker-amp should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up the path of ? dac ? spk-amp ? dacm = alc2s bit: ? 0 ? ? 1 ? (3) set up the alc2 enable/disable (4) set up the digital volume (addr: 0ah) after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (5) power up of dac and speaker-amp: pmdac bit = pmspk bit = ? 0 ? ? 1 ? when alc2 bit = ? 1 ? , the alc2 is disabled (alc2 gain is fiexed to ? ?2db ? ) during the initilization cycle (512/fs = 64ms @ fs=8khz, rotm bit = ? 0 ? ) and the alc2 starts from ? ?2db ? after completing the initilization cycle. (6) exit the power-save-mode of speaker-amp: spps bit = ? 0 ? ? 1 ? ? (6) ? time depends on the time constant of input impedance of min pin and capacitor between min pin and mout pin. if speaker-amp output is enabled before min-amp (alc2) becomes stable, pop noise may occur. e.g. input impedance of min pin =36k ? (max), c=0.1 f: recommended wait time is more than 5 = 18ms. (7) enter the power-save-mode of speaker-amp: spps bit = ? 1 ? ? 0 ? (8) disable the path of ? dac ? spk-amp ? dacm = alc2s bit: ? 1 ? ? 0 ? (9) power down dac and speaker-amp: pmdac bit = pmspk bit = ? 1 ? ? 0 ?
asahi kasei [ak4632] ms0396-e-00 2005/06 - 63 - ? beep signal output from speaker-amp alc2s bit (addr:02h, d5) pmspk bit (addr:00h, d4) beeps bit (addr:02h, d6) spp pin normal output spps bit (addr:02h, d7) hi-z hi-z spn pin normal output hi-z hi-z svdd/2 svdd/2 (3) 0 0 or 1 (1) alc2 bit (addr:07h, d6) (2) (6) (5) pmbp bit (addr:00h, d2) 0 or 1 0 clocks can be stopped. clock (4) (7) example: (2) addr:00h, data:70h (3) addr:02h, data:60h (1) addr:07h, data:00h (4) addr:02h, data:e0h beep signal output (5) addr:02h, data:60h (6) addr:00h, data:40h (7) addr:02h, data:00h figure 52. ? bepp-amp ? speaker-amp ? output sequence the clocks can be stopped when only beep-amp and speaker-amp are operating. however alc2 must be disabled. (1) alc2 disable: alc2 bit = ? 0 ? (2) power up beep-amp and speaker-amp: pmbp bit = pmspk bit = ? 0 ? ? 1 ? (3) disable the path of ? alc2 ? spk-amp ? : alc2s bit = ? 0 ? enable the path of ? beep ? spk-amp ? : beeps bit = ? 0 ? ? 1 ? (4) exit the power-save-mode of speaker-amp: spps bit = ? 0 ? ? 1 ? ? (4) ? time depends on the time constant of external resistor and capacitor connected to beep pin. if speaker-amp output is enabled before input of beep-amp becomes stable, pop noise may occur. e.g. r=20k, c=0.1 f: recommended wait time is more than 5 = 10ms. (5) enter the power-save-mode of speaker-amp: spps bit = ? 1 ? ? 0 ? (6) power down beep-amp and speaker-amp: pmbp bit = pmspk bit = ? 1 ? ? 0 ? (7) disable the path of ? beep ? spk-amp ? : beeps bit = ? 1 ? ? 0 ?
asahi kasei [ak4632] ms0396-e-00 2005/06 - 64 - ? mono lineout 1. in case of using an external mute circuit.(compatible with ak4536/ak4630) fs3-0 bits (addr:05h, d5,d2-0) dvol7-0 bits (addr:0ah, d7-0) pmdac bit (addr:00h, d2) pmao bit (addr:00h, d3) xxxx xxxx 00011000 xxxxxxx aout pin hi-z hi-z (1) (3) (4) (2) daca bit (addr:02h, d4) (6) normal output (5) example: pll, master mode audio i/f format :dsp mode, bckp=msbs= ?0? sampling frequency: 8khz digital volume: -8db (2) addr:02h, data:10h (3) addr:0ah, data:28h (1) addr:05h, data:00h (4) addr:00h, data:4ch (5) addr:00h, data:40h playback (6) addr:02h, data:00h figure 53. mono lineout sequence at first, clocks should be supplied according to ? clock set up ? sequence. (1) set up a sampling frequency (fs3-0 bits). when the ak4632 is pll mode, dac and mono line amp should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up the path of ? dac ? mono line amp ? daca bit: ? 0 ? ? 1 ? (3) set up the digital volume (addr: 0ah) after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (4) power up of dac and mono line amp: pmdac bit = pmao bit = ? 0 ? ? 1 ? when dac and mono line amp are powered-up, the pop noise occurs from aout pin. therefore aout pin should be muted by external circuit. (5) power down of dac and mono line amp: pmdac bit = pmao bit = ? 1 ? ? 0 ? when dac and mono line amp are powered-down, the pop noise occurs from aout pin. therefore aout pin should be muted by external circuit. (6) disable the path of ? dac ? mono line amp ? daca bit: ? 1 ? ? 0 ?
asahi kasei [ak4632] ms0396-e-00 2005/06 - 65 - 2. in case of using pop reduction circuit of ak4632. fs2-0 bits (addr:05h, d5,d2-0) dvol7-0 bits (addr:0ah, d7-0) pmdac bit (addr:00h, d2) pmao bit (addr:00h, d3) xxxx xxxx 00011000 xxxxxxx aout pin (1) (3) (4) (2) daca bit (addr:02h, d4) (9) normal output (6) psaon bit (addr:03h, d6) (5) >300 ms (7) (8) >300 ms (10) example: pll, master mode audio i/f format :dsp mode, bckp=msbs= ?0? sampling frequency: 8khz digital volume: -8db mgain1=spkg1=spkg0=beepa=alc1m =alc1a= ?0? (1) addr:05h, data:00h (2) addr:02h, data:10h (3) addr:0ah, data:28h (4) addr:03h, data:40h (5) addr:00h, data:4ch (6) addr:03h, data:00h playback (7) addr:03h, data:40h (8) addr:00h, data:40h (9) addr:02h, data:00h (10) addr:03h, data:00h figure 54. mono lineout sequence at first, clocks should be supplied according to ? clock set up ? sequence. (1) set up a sampling frequency (fs3-0 bits). when the ak4632 is pll mode, dac and mono line amp should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up the path of ? dac ? mono line amp ? : daca bit: ? 0 ? ? 1 ? (3) set up the digital volume (addr: 0ah) after dac is powered-up, the digital volume changes from default value (0db) to the register setting value by the soft transition. (4) enter power-save mode of mono line amp: aopsn bit = ? 0 ? ? 1 ? (5) power up of dac and mono line amp: pmdac bit = pmao bit = ? 0 ? ? 1 ? aout pin rises up to vcom voltage. rise time is 200ms (max 300ms) at c=1 f. (6) exit power-save mode of mono line amp after aout pin rises up. : aopsn bit = ? 1 ? ? 0 ? mono line amp goes to normal operation. (7) enter power-save mode of mono line amp: aopsn bit = ? 0 ? ? 1 ? (8) power down of dac and mono line amp: pmdac bit = pmao bit = ? 1 ? ? 0 ? aout pin falls down to avss. fall time is 200ms (max 300ms) at c=1 f. (9) disable the path of ? dac ? mono line amp ? : daca bit: ? 1 ? ? 0 ? (10) exit power-save mode of mono line amp after aout pin falls down. : aopsn bit = ? 1 ? ? 0 ?
asahi kasei [ak4632] ms0396-e-00 2005/06 - 66 - ? video signal input and output sagc1-0 bits (addr:0ch, d6-5) pmv bit (addr:01h, d7) x x x x vout pin avss avss (2) (3) normal output vgca4-0 bits (addr:0ch, d4-0) x x x x x x x x x x (4) pmvcm bit (addr:00h, d6) clocks x 1 clocks can be stopped, if only video output is enable. (1) example: audio function :no use pll master mode video output : dc output vgca : 0db ( 3 ) addr:01h, data:8bh video output (2) addr:0ch, data:02h ( 4 ) addr:01h, data:0bh ( 1 ) addr:00h, data:45h figure 55. video output sequence when the only video function is used, the clocks are not needed to input. (1) power up of vcom : pmvcm bit = ? 0 ? ? 1 ? (2) set up the output circuit(sagc1-0bits) and gca(vgca4-0 bits) (3 ) power up of video-amp : pmv bit = ? 0 ? ? 1 ? the video signal that is input to vin pin starts output from vout pin. (4) power down of video-amp : pmv bit = ? 1 ? ? 0 ? the output from vout pin stops. vout pin goes to avss. if any audio f unctions are not used, vcom can be powered-down(pmvcm bit = ? 0 ? )
asahi kasei [ak4632] ms0396-e-00 2005/06 - 67 - ? stop of clock master clock can be stopped when adc, dac, alc1, alc2 and ipga don?t operate. 1. in case of pll master mode mckpd bit (addr:01h, d2) external mcki pmpll bit (addr:01h, d0) mcko bit (addr:01h, d1) input (4) (1) (2) (3) "h" or "l" example: audio i/f format: dsp mode, bckp = msbs = ?0? bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz sampling frequency:8khz stop an external mcki (1) (2) (3) addr:01h, data:0ch figure 56. clock stopping sequence (1) (1) power down pll: pmpll bit = ? 1 ? ? 0 ? (2) stop mcko clock: mcko bit = ? 1 ? ? 0 ? (3) pull down the mcki pin: mckpd bit = ? 0 ? ? 1 ? when the external master clock becomes hi-z, mcki pin should be pulled down. (4) stop an external master clock. 2. when an external clocks (fck or bick pins) are used in pll slave mode. external bick pmpll bit (addr:01h, d0) input (1) (2) external fck input (2) example audio i/f format : dsp mode, bckp = msbs = ?0? pll reference clock: bick bick frequency: 64fs sampling frequency: 8khz (1) addr:01h, data:04h (2) stop the external clocks figure 57. clock stopping sequence (2) (1) power down pll: pmpll bit = ? 1 ? ? 0 ? (2) stop the external bick and fck clocks
asahi kasei [ak4632] ms0396-e-00 2005/06 - 68 - 3. when an external clock (mcki pin) is used in pll slave mode. external mcki pmpll bit (addr:01h, d0) input (1) (2) mcko bit (addr:01h, d1) (1) mckpd bit (addr:01h, d2) (1) example audio i/f format : dsp mode, bckp = msbs = ?0? pll reference clock: mcki bick frequency: 64fs sampling frequency: 8khz (1) addr:01h, data:04h (2) stop the external clocks figure 58. clock stopping sequence (3) (1) power down pll: pmpll bit = ? 1 ? ? 0 ? stop mcko output: mcko bit = ? 1 ? ? 0 ? pull down the mcki pin: mckpd bit = ? 0 ? ? 1 ? when the external master clock becomes hi-z, mcki pin should be pulled down. (2) stop the external master clock. 4. ext slave mode mckpd bit (addr:01h, d2) external fck input (2) (1) external bick input (2) external mcki input (2) example audio i/f format :msb justified(adc and dac) input mcki frequency:1024fs sampling frequency:8khz (2) stop the external clocks (1) addr:01h, data:04h figure 59. clock stopping sequence (4) (1) pull down the mcki pin: mckpd bit = ? 0 ? ? 1 ? when the external master clock becomes hi-z, mcki pin should be pulled down. (2) stop the external mcki, bick and fck clocks. ? power down if the clocks are supplied, power down vcom (pmvcm bit: ? 1 ? ? 0 ? ) after all blocks except for vcom are powered-down and a master clock stops. the ak4632 is also powered-down by pdn pin = ? l ? . when pdn pin = ? l ? , the registers are initialized.
asahi kasei [ak4632] ms0396-e-00 2005/06 - 69 - package 32pin qfn (unit: mm) 4.75 0.10 5.00 0.10 4.75 0.10 0.50 0.23 24 17 25 1 16 1 0.01 0.08 32 8 9 c0.42 32 +0.07 -0.05 0.40 0.10 0.20 + 0.04 - 0.01 c exposed pad 3.5 5.00 0.10 0.85 0.05 c b a 0.10 m ab 3.5 note) the exposed pad on the bottom surface of the package must be open. ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [ak4632] ms0396-e-00 2005/06 - 70 - marking 4632 x xxx 1 xxxx : date code identifier (4 digits) revision history date (yy/mm/dd) revision reason page contents 05/06/01 00 first edition important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, an d akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefor e meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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